Verilog/VHDL grammar learning is a mastery of basic code design skills and experience

There are many ways to design input for an FPGA/CPLD device, such as drawing a schematic, writing code, or calling an IP core. Early engineers had a special liking for the design of schematics. This kind of input method can handle simple logic circuits. It should be simple and practical, but as the scale of logic continues to rise, this backward design method has become inadequate. . Instead of code input, most of today's designs use code to do it.

The code used in FPGA/CPLD development is commonly referred to as the Hardware Description Language. The most mainstream ones are VHDL and Verilog. VHDL develops earlier and has a grammatical rigor; Verilog is similar to C language, and its grammatical style is relatively free. IP core calls are usually based on code design input. Today, many EDA tool vendors are working on FPGA/CPLD's wishful thinking. FPGA/CPLD design is also developing towards software and platform. Maybe in In the near future, more and more projects will only require designers to request components from an IP library like the Apple Store for configuration, and finally complete a project like building blocks, or the entire design does not need to see a code. Of course, any situation may happen in the future, but the underlying code logic writing method still has its living space anyway. After all, each IP core component starts from the code, so for the newcomer who is new to the business. Mastering the skills of basic code design is a must.

We don't talk much about VHDL and Verilog languages. In short, these two languages ​​are the languages ​​used in most of the current development and design. From the two descriptions and implementations of circuits, there are many similarities. Whether it is VHDL or Verilog, it is recommended that beginners master one of them first. As for which one to start with, you need to consider the situation according to your own situation. For friends who have no external restrictions, if you have a certain C language foundation before, you may want to learn Verilog first, which helps to speed up the understanding of the grammar itself. After learning and using one of the languages, it is best to start another language. Although in a single project, you rarely need to be “bilingually bilingual”, in actual work, it is very likely that you need to touch the project written by another grammar. There are many good open source examples on the network. If you only have Verilog and the reference instance is VHDL, then it will make you very embarrassed. Suddenly one day A colleague left, the boss threw his half-written Verilog project to Only VHDL you maintain, then you are passively embarrassed... So, for the trade-off between VHDL and Verilog, it is recommended to learn one first, and don’t forget the other, no matter which language, At the very least, you should be able to understand other people's designs.

Although the HDL language has many similarities with the software language, since the implementation object is a hardware circuit, the design ideas between them are quite different. Especially those who have done software programming, I like to drive the HDL language with the sequential idea of ​​software. I don't know that the hardware circuits implemented by HDL are mostly processed in parallel. Perhaps it is such a big turn, so many friends are often puzzled when studying the functions implemented by the HDL language. For beginners, especially beginners who turn software over, the author's suggestion is not to study the grammar without throwing away the actual circuit. After a piece of code, spend more energy on the actual logic circuit, if necessary, do simulation, preferably Look for some intuitive peripherals to see the results on the board. In the long run, if you can achieve both the code and the circuit, it will prove that you are really mastering the essence of the HDL language.

Although there are many grammatical entries in the HDL language, not all HDL grammars can be implemented into the final hardware circuit. The division can be implemented as the syntax of the hardware circuit. We often call it synthesizable syntax, but not hardware. In the circuit, it is often used as a high-level syntax for simulation verification. We call it behavior-level grammar. Many friends used a grammar book to look at the grammar when they first started learning. At the end of the actual battle, they often encountered that the grammar could not use the error message that the grammar did not support, and thus complained that HDL is not a good thing, and it is really difficult to learn. In fact, the synthesizable grammar is a small subset. For beginners, it is recommended to focus on mastering this subset first. In actual design, perhaps 10 basic grammars can be used to fight the world. How? The HDL language has become simpler. It's no exaggeration to say this, the focus of this book is to quickly learn how to use a synthesizable subset of grammars to complete a design through a variety of routines that can be implemented at the board level. In the next section, we will list the commonly used synthesizable grammars one by one and briefly introduce them.

For the students who have entered the door, it is not to say that mastering the comprehensive grammar subsets is all right, saying that "the revolution has not been successful, and comrades still need to work hard." Behavioral grammar is also useless. It is said that "existence is reasonable" and behavioral grammar is also useful. A slightly more complicated design, if it is not tested several times before the board level debugging, the probability of one-time success is almost zero. The simulation verification also has its own set of efficient and convenient syntax. If you build a simulation platform like the underlying hardware circuit, I am afraid it will be a waste of time. The final implementation object of the behavior-level grammar is not the FPGA/CPLD device, but the computer in the hands of the ,, G or even dual-core, quad-core CPU can not do the work of the old cow, so the behavioral grammar helps us in the simulation process. By utilizing the resources in your hands, you can quickly and efficiently complete the initial verification platform for design. Therefore, mastering the behavioral grammar can serve our work in the simulation verification phase of the design. To say more, everyone should not faint, this book focuses on comprehensive grammar, is also the focus of assault for beginners, behavioral grammar is the pursuit of higher level design, as a beginner, you can slow down, saying "first walk and then Learn to fly" Well.

For the learning of HDL language, the author proposes several suggestions based on his own experience.

First of all, you need to prepare a relatively complete grammar book. These books are already flying in the market, and the content is almost the same. It is best for beginners to take some time to read the grammar carefully before starting the FPGA/CPLD. Understand as much as possible the basic functions and usage of each grammar. Of course, you only need to have carefully read and understood it. If you have the relevant grammar, you will not be able to cope with the exam, nor will you have to memorize anything. The theoretical study of grammar is a must, and can lay a solid foundation for later practice. Some grammars that are really difficult to understand, don't force them. In the future, it will not be too late to encounter similar grammar reference usage in the examples.

Second, refer to some simple routines and write the code yourself to achieve the same or similar circuit functions. This process may require a combination of actual FPGA/CPLD development tools and an entry-level learning suite. The FPGA/CPLD development tools have been introduced in the previous chapters, mainly to master the use of Quartus II (Altera's device use) or ISE (Xilinx device use), learn to use these tools to create a new project, write code, distribution tube Foot, compile, download the configuration file to the target board. The entry-level learning kit, to put it simply, is the board of an onboard FPGA/CPLD device. This board does not require many advanced peripherals, and some simple common peripherals (such as buzzer, water) Lights, digital tubes, UART, IIC, etc.); a download line and associated Cable. Through the development tools we can build and manage the project; and with the learning suite, we can visually verify that the project has achieved the intended function. In the process of practice, you must pay attention to your own code style, of course, which depends largely on the code style of the reference routine. As for what kind of learning kit supporting reference routines are normative, there is no definition. When you suggest that you choose a better learning kit, you are also recommended to read the FPGA/CPLD original Altare. (qts_qii5v1.pdf) or Xilinx (xst.pdf) official documentation, in some of their documentation manuals have a variety of common circuit implementation code styles and reference examples. In the course of the exercise, you should also learn to use the various tools produced by the development tools, especially the RTL view. The RTL view is a logical function view that integrates the user input code. This view is a good way to interpret the user's code in a logic gate. Beginners can look at the RTL view to see how the code they write can be implemented. The logic circuit to deepen the understanding of the grammar; conversely, the RTL view can also be used to verify whether the currently written code achieves the desired function.

In short, the learning of HDL language, simple induction, is the need for beginners to see more, write more, think more, compare.