Before going into this section, let's review Part 1: Brushless DC motors are cool (can help you make friends); no one likes to talk about actual hardware (but I plan to do this); discrete and integrated gates Drivers have their own advantages and disadvantages. I can talk about features and benefits all day, but the engineers want to see some real circuits. In this blog post, I will directly compare the discrete and integrated gate drive architectures to show the board-level differences between the two. Two key metrics for schematic and layout comparison are component count and solution size. The first metric is: Number of components. This can be found relatively easily after the schematic is complete. However, the estimation of the solution size is more complicated. I often see solution sizes that are simply labeled on the dimensions of integrated circuit components. But I found this to be very inaccurate because it did not take into account the gaps required between the external components, the components and the wiring on the board. I spent some time on local design software to create parallel schematics and layouts for discrete and integrated gate driver architectures for brushless DC motor drives. I chose TI's discrete gate driver and the DRV8320 ​​as my integrated gate driver. In addition, I used a standard QFN package of NexFETTM power MOSFETs. Although this design happens to use standard discrete FETs, TI recently introduced two vertically integrated half-bridge power blocks for this application, saving more design space. This application puts pressure on my poor circuit diagrams and layout techniques, but I hope that these images will help those who want to compare the two brushless DC architectures. This seemingly quick-impact project injects a lot of design and ideas. As you can guess from the above, to simplify browsing, I decided to create a two-layer board without an inner layer. However, this means that more effort is required on the layout. Similarly, the gate drive setup component on the discrete gate driver and the IDRIVE pin component on the integrated gate driver need to be adjusted to achieve acceptable rise and fall times from the external FET. There are also many small adjustments in the layout section to achieve the minimum size of both solutions.
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