Build complex broadband wireless system receivers in Xilinx Virtex-5 devices with AutoESL advanced synthesis tools. Space division multiplexing MIMO processing technology can significantly improve the spectrum efficiency of wireless communication systems, thereby greatly increasing the capacity of wireless communication systems. For this reason, it has become a core component of the new generation of WiMAX and other OFDM-based wireless communication systems. Space division multiplexing MIMO processing is a computationally intensive application that enables highly demanding signal processing algorithms. In a MIMO system, a specific example of a space division multiplexing technique is sphere decoding. Spherical decoding is an effective method to solve the MIMO detection problem, which is comparable to the best maximum likelihood detection algorithm in terms of bit error rate (BER) performance. However, the DSP processor has limited computing power and is not sufficient to meet the real-time requirements of spherical decoding. Field Programmable Gate Array (FPGA) is an attractive platform for implementing complex DSP-intensive algorithms such as sphere decoders. Modern FPGAs are high-performance parallel computing platforms that provide the system with the specialized hardware needed while maintaining the flexibility of a programmable DSP processor. A number of studies have shown that in multiple signal processing applications, FPGA performance is 100 times higher than traditional DSP processors, and the price/performance ratio can be increased by 30 times. Although the performance of FPGAs has considerable advantages, it is generally not applicable to wireless signal processing, mainly because traditional DSP programmers think they are not easy to handle. In fact, the real impediment to making FPGAs unusable in wireless applications is hardware-centric traditional design processes and tools. At present, to use FPGA to design, you need a wealth of hardware design experience, including familiar with hardware description languages ​​such as VHDL and Verilog. Recently, new advanced synthesis tools can be used as an auxiliary design tool for FPGAs. These design tools take advanced algorithmic descriptions as inputs and generate RTLs that can be used with standard FPGA implementation tools such as the Xilinx® ISE® design suite and embedded development kits. This tool increases design efficiency, reduces development time, and enables high-quality design. We can use this tool to design FPGA-based complex wireless algorithm applications, namely the space division multiplexing MIMO sphere detector under 802.16e system. We chose AutoESL's AutoPilot advanced synthesis tool as an auxiliary design tool for the Xilinx Virtex®-5 with a clock frequency of 225MHz. Sphere decoding As part of the decoding process, sphere detection is an effective method for simplifying the detection complexity of space division multiplexing systems. It is comparable to the more complex best maximum likelihood (ML) detection algorithm in terms of BER performance. As shown in Figure 1, in the block diagram of the MIMO 802.16e radio receiver, we assume that the receiver can accurately estimate the channel matrix, which can be achieved by the traditional channel estimation method. The pipeline of this implementation has three building blocks: channel reordering, QR decomposition, and a spherical detector (SD). We generate soft outputs by calculating the detected bit-log likelihood ratio (LLR) to prepare for the use of soft-input, soft-output channel decoders such as turbo decoders. Figure 1 Block diagram of the sphere decoder Channel matrix reordering The order in which the spherical detector processes the antenna can have a large impact on the performance of the BER. Before performing the sphere detection, channel reordering is first performed. The detector uses a channel matrix preprocessor to implement a continuous interference cancellation processing technique similar to that used in the Bell Labs Layered Space-Time (BLAST) architecture, which ultimately achieves near-ML performance. The method is implemented by channel reordering processing, and the optimal column detection order of the complex channel matrix is ​​determined by multiple iterations. The algorithm selects the row with the largest or smallest norm based on the number of iterations. The line with the smallest Euclidean norm indicates that the antenna has the strongest influence, while the line with the largest Euclidean norm indicates that the antenna has the weakest influence. This novel approach first deals with the weakest data stream, and then iteratively processes the data streams from high to low. In order to meet the application's high data rate requirements, we implemented the pipeline architecture based channel ordering module shown in Figure 2. The module can process 5 channels simultaneously in Time Division Multiplexing (TDM) mode. This approach extends processing time between different matrix elements on the same channel while maintaining high data throughput. Figure 2 Iterative channel matrix reordering algorithm This method performs complex rotations of diagonal and non-diagonal units, which are the basic computational units of the pulsating array we use. After the improved real matrix QRD obtains the best ordering of the channel matrix columns, the next step is to perform QR decomposition on the real matrix coefficients. The functional unit used for this QRD processing is similar to the QRD engine that computes the inverse matrix, but with some differences. The input data for this example is a real number, so the dimension of the pulsating array structure will be correspondingly higher (ie 8&TImes; 8 real values ​​instead of 4 & TImes; 4 complex values).
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In Figure 2, the G matrix calculation is the most demanding component. At the heart of the process is matrix inversion, which can be achieved by QR decomposition. A common way to implement QRD is to use Givens rotation. 