Four important PCB layout rules when using high speed converters

Regarding PCB design, an engineer has 10,000 words to say, whether it is experience or spit, or PCB design anecdote that has happened. Of course, we will also see the documents shared by various experiences. I don't know how everyone can look at the rules and experience of PCB design.

Today, Xiaobian wants to share with you the super material, summarized by Rob Reeder, senior system application engineer of ADI Industrial and Instrumentation Department [four important PCB layout rules when using high-speed converters]. Four classic questions to help you get less detours on the PCB design road

Should the AGND and DGND ground planes be separated?

The simple answer is: depending on the situation; the detailed answer is: usually not separated.

Because in most cases, separating the ground plane will only increase the inductance of the return current, which brings more harm than good. As can be seen from the formula V = L(di/dt), as the inductance increases, the voltage noise increases. As the switching current increases (because the converter sampling rate increases), the voltage noise also increases. Therefore, the ground planes should be connected together.

An example is that in some applications, in order to comply with traditional design requirements, dirty bus power or digital circuits must be placed in certain areas, and also affected by size limitations, making the board unable to achieve good layout segmentation. In this case, separating the ground plane is the key to achieving good performance. However, in order for the overall design to be effective, these ground planes must be connected together through a bridge or connection point somewhere on the board. Therefore, the connection points should be evenly distributed on separate ground planes. Eventually, there will often be a connection point on the PCB that is the best place for return current to pass without causing performance degradation. This connection point is usually located near or below the converter.

When designing the power plane, all copper wires that can be used by these layers should be used. If possible, do not allow these layers to share the traces, as additional traces and vias divide the power plane into smaller pieces that quickly damage the power plane. The resulting sparse power plane can squeeze the current path to where it is most needed, the power supply pin of the converter. Squeezing the current between the via and the trace increases the resistance, causing a slight voltage drop across the converter's power supply pin.

Finally, the placement of the power plane is critical. Do not place high-noise digital power supplies on the analog power plane. Otherwise, although they are on different layers, they may still be coupled. To minimize the risk of system performance degradation, these types of layers should be separated as much as possible in the design.

Can the PCB's power transmission system (PDS) design be ignored?

The PDS is designed to minimize voltage ripple generated in response to supply current requirements. All circuits require current, some require more circuitry, and some require current at a faster rate. With a fully decoupled low-impedance power or ground plane and good PCB stacking, voltage ripple due to the current requirements of the circuit can be minimized. For example, if the designed switching current is 1A and the PDS impedance is 10mΩ, the maximum voltage ripple is 10mV.

First, a PCB stack structure that supports a larger layer of capacitance should be designed. For example, a six-layer stack may include a top signal layer, a first ground layer, a first power layer, a second power layer, a second ground layer, and a bottom signal layer. It is prescribed that the first ground layer and the first power layer are close to each other in the stacked structure, and the two layers are spaced apart by 2 to 3 mils to form a laminar layer capacitance. The biggest advantage of this capacitor is that it is free and only needs to be noted in the PCB manufacturing notes. If the power plane must be split and there are multiple VDD rails on the same layer, the largest possible power plane should be used. Don't leave holes, but also pay attention to sensitive circuits. This will maximize the capacitance of the VDD layer. If the design allows for the presence of additional layers (in this case, from six to eight), then two additional ground planes should be placed between the first and second power planes. In the case where the core pitch is also 2 to 3 mils, the inherent capacitance of the laminated structure at this time is doubled.

For ideal PCB stacking, decoupling capacitors should be used at the power supply layer start entry point and around the DUT, which will ensure that the PDS impedance is low over the entire frequency range. Using a few 0.001μF to 100μF capacitors helps cover this range. It is not necessary to configure the capacitors everywhere; the capacitors facing the DUT will destroy all manufacturing rules. If such severe measures are required, there are other problems with the circuit.

How do you achieve the best electrical and thermal connection to the exposed pad?

This is an easy to overlook aspect, but it is critical to achieving the best performance and heat dissipation in PCB design.

The exposed pad (Pin 0) refers to a pad under most modern high-speed ICs. It is an important connection through which all internal grounding of the chip is connected to the center point below the device. The presence of an exposed pad allows many converters and amplifiers to eliminate the need for a ground pin. The key is to form a stable and reliable electrical connection and heat dissipation connection when soldering the pad to the PCB, otherwise the system may be seriously damaged.

The best electrical and thermal connection to the exposed pad can be achieved through the following three steps -

0 1

Where possible, the exposed pad should be replicated on each PCB layer, which will provide a thicker thermal connection for all grounds for fast heat dissipation, especially for high power devices. On the electrical side, this will provide a good equipotential bonding for all ground planes. When the exposed pad is replicated on the bottom layer, it can be used as a decoupling ground point and where the heat sink is mounted.

0 2

The exposed pad is divided into multiple identical parts. It is best in a checkerboard shape and can be achieved by a wire mesh cross grill or a welding hood. During the reflow assembly process, it is not possible to determine how the solder paste flows to establish the connection of the device to the PCB, so the connections may be present but not evenly distributed, and even worse, the connections are small and located at the corners. Dividing the exposed pad into smaller sections allows each area to have a connection point to ensure a reliable, uniform connection between the device and the PCB.

0 3

It should be ensured that each part has a via to the ground. Each area is usually large enough to hold multiple vias. It is important to fill each via with solder paste or epoxy before assembly. This is important to ensure that the exposed pad solder paste does not flow back into the via hole, which would reduce the chance of proper soldering.

Does cross-coupling between layers in the PCB really matter?

In PCB design, the layout of some high-speed converters inevitably occurs when one circuit layer overlaps with the other. In some cases, a sensitive analog layer (power, ground, or signal) may be directly above the high-noise digital layer. Because these layers are on different layers, it doesn't matter? Let's look at a simple test.

Select one of the adjacent layers and inject a signal at that level. The cross-coupling layer is then connected to a spectrum analyzer. It can be seen that there are many signals coupled to adjacent layers. Even with a 40 mil spacing, in some sense adjacent layers still form a capacitor, so at some frequencies the signal will still couple from one layer to another.

Assuming that the high-noise digital portion of a layer has a high-speed switching 1V signal with an interlayer isolation of 60dB, the undriven layer will see the 1mV signal coupled from the driven layer. For a 12V analog-to-digital converter (ADC) with 2Vp-p full-scale swing, this means a coupling of 2LSB (least significant bit). This may not be a problem for a particular system, but it should be noted that when the resolution is increased from 12 bits to 14 bits, the sensitivity is increased by a factor of four and the error is increased to 8 LSB.

Ignoring cross-over/cross-layer coupling may not cause system design failure or weaken the design, but must be vigilant because the coupling between the two layers may be more than expected.

This should be noted when noise stray coupling is found in the target spectrum. Sometimes, place and route can cause unintended signals or layers to cross-couple to different layers. Keep this in mind when debugging sensitive systems: the problem may be at the next level.