1. The basic structure of an embedded microprocessor (1) Embedded hardware systems generally consist of an embedded microprocessor, memory, and input/output sections. (2) The embedded microprocessor is the core of the embedded hardware system, usually composed of the control unit, the arithmetic logic unit and the register 3: A. Control unit: Mainly responsible for basic operations such as fetching, decoding and taking, and sending the main control commands. B. Arithmetic logic unit: mainly processes numerical data and performs logical operations. C, register: used to temporarily store temporary data. 2. Classification of embedded microprocessors (depending on usage) (1) Embedded Microcontroller (MCU): Also known as single-chip microcomputer, the on-chip peripheral resources are generally rich and suitable for control. The biggest feature is singularity, small size, low power consumption and low cost, and high reliability. Currently accounts for about 70% of the market. (2) Embedded Microprocessor (EMPU): Also known as a single board computer, it is developed from a CPU in a general-purpose computer. It is characterized by a processor with more than 32 bits and high performance. Usually the embedded microprocessor puts the CPU, ROM, RAM and I/O modules on the same chip. (3) Embedded DSP processor (DSP): A processor specially designed for signal processing. It is specially designed in terms of system structure and instruction algorithm, making it 10 to 50 times faster than the fastest CPU. A large number of applications have been obtained in digital filtering, FFT, and spectrum analysis. (4) Embedded system-on-a-chip (SOC): The integrated device that pursues the maximum inclusiveness of the product system, its biggest feature is the successful realization of the seamless integration of software and hardware, directly embedded in the microprocessor chip code module of the operating system. 3. Typical microprocessor structure and features (1) 8-bit microprocessor: Focus on the 8051, thoroughly understand the working principle of 8-bit microcontroller, peripheral control, memory distribution, addressing mode and typical applications. (2) 16-bit microprocessor: A typical microprocessor can refer to MSP430. Find a book on this subject to see the structure and typical application of the MSP430. (3) 32-bit microprocessor: The 32-bit processor uses a 32-bit address and data bus, and its address space reaches 2 32 = 4GB. At present, the mainstream 32-bit embedded processor systems mainly include the ARM series, the MIPS series, and the PoewrPC series. The ARM microprocessor architecture is currently recognized as the leading 32-bit embedded RISC processor architecture for embedded applications. According to current developments, ARM is almost synonymous with embedded applications. 4, the basic concept of the microcontroller system (1) The composition of the single-chip microcomputer: central processing unit, memory, I/O equipment. (2) Memory: Physically, one or more sets of integrated circuits with data input/output and data storage functions, used to act as a device cache or to store fixed programs and data. A, ROM (Read Only Memory): Generally used to store fixed programs or data tables, etc., data will remain after power down. B, RAM (random memory): used to temporarily store programs and data, intermediate calculation results, or used as a stack, etc., data will be lost after power failure. (3) I/O port: A channel that the MCU communicates with the outside world. It can detect, judge, and process various external signals (switching quantity, analog quantity, frequency signal), and can control various external devices. Today's microcontroller I/O ports have integrated more features and functions, expanding and multiplexing I/O ports, such as external interrupts, ADC detection, and PWM outputs. (4) Output level: high level voltage (when outputting "1") and low level voltage (when outputting "0") A, TTL level: positive logic, 5V is logic positive, 0V is logic negative, such as the output of the microcontroller. B, RS232 level: negative logic, -12V is logic positive, +12V is logic negative, such as PC output. Note: Therefore, a MAX232 chip is required for level conversion when the microcontroller and the PC communicate. (5) Stack: It is a linear data structure, which is a one-dimensional space with only one import and export. A, stack characteristics: last in, first out (LIFO) B. Stack pointer: used to indicate the position (address) of the top of the stack. When a push or pop operation occurs, the stack pointer changes as the top position of the stack changes. C, stack operations: push operation (PUSH) and pop operation (POP). D, stack type: "up-growth" type stack, the stack pointer is incremented by 1 each time the stack is pushed; the "down-growth" type stack is decremented by 1 each time the stack is pushed. E. Stack application: When calling a subroutine, responding to an interrupt, the stack is used to protect the scene; it can also be used as a temporary data buffer. F, use note: stack overflow problem, push stack and pop stack matching problem. (6) Timing counter: The essence is all counters. When used as a timer, it counts the internal clock pulse of the microcontroller, and when used as a counter, it counts the input pulse external to the microcontroller. Its function is as follows: A, timing, timing or delay control; B, pulse technology; C, measuring pulse width or frequency (capture function) (7) Interrupt: A higher priority event occurs, interrupting the time process with a lower priority. The event that caused the interrupt is called the interrupt source. A single-chip microcomputer may support multiple interrupt sources. These interrupt sources can be divided into maskable interrupts and non-maskable interrupts. These interrupt sources are not required for system operation. We can shield those interrupt sources that are not needed according to system requirements. . A. Interrupt nesting: When a low-level interrupt has not been executed yet, a high-priority interrupt occurs, and the system executes the advanced interrupt service routine. After the high-level interrupt is processed, it goes back to execute the low-level interrupt service routine. B. The interrupt response time refers to the time from the issuance of the interrupt request to the entry of the interrupt processing; the interrupt processing time refers to the time from the start of the interrupt processing to the end of the interrupt processing. C, interrupt response process: a. Protect the scene: save the current address, accumulator ACC, and status register to the stack. b. Switch the PC pointer: switch to the corresponding entry address according to the interrupt generated by different interrupt sources. c. Execute the interrupt service handler. d. Restore the scene: Restore the main program address, accumulator ACC, and status register saved in the stack. e, interrupt return: return from the interrupt to the main program, continue to execute. D. Interrupt Ingress Address: The MCU allocates different interrupt entry addresses for each interrupt source, also known as interrupt vectors. (8) Reset: Introduce a reset signal to the reset of the microcontroller through an external circuit to let the system restart. A. Action when reset occurs: a, the PC pointer starts from the starting position (most microcontrollers start from 0x0000). b. The I/O port is set to the default state (high impedance state, or output low level). c. Part of the dedicated control register SFR is restored to the default state. d, the normal RAM is unchanged (if the power-on reset, it is random). B. Two different reset start modes: a, cold start: also called power-on reset, refers to powering up the system in the power-off state, so that the system starts normal operation. b. Hot start: In the state of uninterrupted power, a reset signal is introduced to the reset of the single-chip microcomputer to let the system start again. C. Two types of reset circuits: high level reset and low level reset. D Note: a. Note that the level state and duration of the reset signal must meet the system requirements. b. Take care to avoid reset signal jitter. (9) Clock circuit: The single chip microcomputer is a kind of sequential circuit, and the pulse circuit must be provided to work normally. The clock circuit is equivalent to the heart of the single-chip microcomputer, and each beat (vibration beat) controls the working rhythm of the single-chip microcomputer. When the oscillation is slow, the system works at a slow speed. When the oscillation is fast, the system works faster (the power consumption also increases). A. Oscillation period: The oscillation tempo of the oscillation source. B. Machine cycle: The oscillation period (beat) required by the MCU to complete a basic operation. C. Instruction cycle: It takes several machine cycles to execute one instruction. Different instructions require different machine cycles. 5, the basic concept of the ARM architecture (1) ARM: Advanced RISC Machine. (2) Two instruction sets are supported in the ARM architecture: the ARM instruction set and the Thumb instruction set. (3) The ARM core has four functional modules: T, D, M, and I: A, T module: represents 16-bit Thumb, which can reduce the code size while balancing performance. B, D module: indicates Debug, the structure for debugging is placed in the kernel, usually a boundary scan chain JTAG. C, M module: represents an 8-bit multiplier. D, I module: Indicates EmbeddedICE Logic, the part of the logic circuit used for real-time breakpoint observation and variable observation. (4) ARM processors have 7 modes of operation: A. User mode: Normal program execution mode for applications. D. Fast Interrupt Mode (FIQ): Fast interrupt processing for high speed data transmission and channel processing. C. External Interrupt Mode (IRQ): Used for general purpose interrupt processing. D. Management Mode (SVE): A protection mode used by the operating system. E, data access abort mode (Abort): for virtual storage and storage protection. F. Undefined instruction abort mode (Undefined): Enter this mode when the instruction is not defined. G, system mode (System): used to run privileged operating system tasks. In addition to the user mode, the other six processor modes are called privileged mode. In these modes, the program can access all system resources, and can also arbitrarily switch the processor mode. Among them, except the system mode, other 5 The privileged mode is also called the abnormal mode. The processor mode can be switched by software control or by external interrupt or exception handling. Most user programs run in user mode. At this time, the application cannot access some system resources protected by the operating system, and the application cannot directly switch between processor modes. When a processor mode switch is required, the application can generate exception handling and switch the processor mode during exception handling. This architecture allows the operating system to control the resources of the entire system. When an abnormal interrupt occurs in the application, the processor enters the corresponding exception mode. In each exception mode, there is a set of registers for use by the corresponding exception handler, so that when the exception mode is entered, the registers in user mode are not destroyed. The system mode is not entered through the exception process. It has exactly the same register as the user mode, but the system mode is privileged mode, which can access all system resources, or directly switch the processor mode. It is mainly used by operating system tasks. . (5) ARM processor has 37 registers: 31 general-purpose registers and 6 status registers A, general-purpose registers include R0~R15, which can be divided into three categories: a, no backup registers R0~R7: In all processor modes, the unbackup registers are all pointing to the same physical register. b, backup register R8 ~ R14: For R8 ~ R12, each register for two different physical registers, each time they access the physical registers are related to the current processor operating mode. For R13, R14, each register is shared by 6 different physical registers, one of which is user mode and system mode. R13 is often used as a stack pointer in ARM instructions. Since each mode of operation of the processor has its own independent physical register R13, all of the initialization parts of the user application typically initialize R13 in each mode to point to the stack space of the run mode. R14, also known as the connection register (LR), has the following two special functions in the ARM system: when the subroutine is called by the BL or BLX instruction, the return address of the current subroutine is stored; when the exception interrupt occurs, the exception mode is stored. The returned address. c. Program counter R15 (PC). Since ARM uses a pipeline mechanism, in a three-stage pipeline, when the value of the PC is correctly read, the value is the current instruction address value plus 8 bytes. That is, the PC points to the address of the next two instructions of the current instruction. In the ARM instruction state, the 0 and 1 bits of the PC are 0. In the Thumb instruction state, the 0 bit of the PC is 0. B, program status register a. The ARM architecture consists of a current Program Status Register (CPSR) and five backed Up Program Status Registers (SPSRs) that are set and read using the MSR and MRS instructions. b. Current Program Status Register CPSR: Information that holds the current processor status and can be accessed in any processor mode. c. Backup Program Status Register SPSR: There is a dedicated physical status register for each exception handler mode. When a specific exception interrupt occurs, this register is used to store the contents of the current program status register. When the abnormal interrupt program exits, the value stored in the SPSR can be used to recover the CPSR. d. Since user mode and system mode are not in abnormal mode, they do not have SPSR. When accessing SPSR in these two modes, the result is unknown. (6) Addressing mode of ARM instructions The so-called addressing mode is the way the processor looks for a physical address based on the address information given in the instruction. A. Immediate addressing: The operand itself is given in the instruction, and the operand is fetched as soon as the instruction is fetched. ADD R0, R0, #1 ; R0=R0+1 B. Register Addressing: Use the value in the register as the operand. ADD R0, R1, R2 ; R0=R1+R2 C. Register Indirect Addressing: The value in the register is used as the operand address, and the operand itself is stored in the memory. ADD R0, R1, [R2] ; R0=R1+[R2]LDR R0, [R1] ; R0=[R1]STR R0, [R1] ;[R1]=R0 D. Base Address Index Addressing: The contents of the register (generally referred to as the base register) are added to the address offset given in the instruction to obtain the effective address of an operand. LDR R0, [R1, #4] ; R0=[R1+4]LDR R0, [R1, #4]! ;R0=[R1+4] R1=R1+4LDR R0, [R1], #4 ;R0 =[R1] R1=R1+4LDR R0, [R1, R2]! ;R0=[R1+R2] E, multi-register addressing: an instruction can complete the transfer of multiple register values. LDMIA R0, {R1, R2, R3} ; R1=[R0] R2=[R0+4] R3=[R0+8] F. Relative addressing: The current value of the program counter PC is used as the base address, and the address label in the instruction is used as the offset. When the two are added, the effective address of the operand is obtained. BL NEXT ; jump to subroutine NEXT to execute...NEXT...MOV PC, LR ; return from subroutine G, stack addressing: support 4 types of stack working mode: a. Full-increment stack: The stack pointer points to the last pushed data and grows from the low address to the high address. b. Full decrement stack: The stack pointer points to the last pushed data and grows from the high address to the low address. c. Empty incremental stack: The stack pointer points to the next empty location where data will be placed and grows from the low address to the high address. d. Empty decrement stack: The stack pointer points to the next empty location where data will be placed, and grows from a high address to a low address. (7) ARM storage method A, big endian mode: The high byte of data is stored in the low address, and the low byte is stored in the high address. B, little endian mode: The low byte of data is stored in the low address, and the high byte is stored in the high address. (8) ARM interrupts and exceptions A, ARM core supports 7 kinds of interrupts, different interrupts are in different processing modes, have different priorities, and each interrupt has a fixed interrupt address entry. When an interrupt occurs, the corresponding R14 (LR) stores the interrupt return address, and the SPSR stores the value of the current program status register CPSR. B. Since the ARM core supports pipeline operation, the address stored in the LR register may be the address of the instruction following the interrupt. Therefore, after the different interrupt processing is completed, the LR register value must be processed before writing to the P15 (PC) register. The specific meaning of C and ARM exceptions: a. Reset: When the reset level of the processor is valid, a reset exception is generated, and the program jumps to the exception reset exception handler. b. Undefined instruction: When an ARM processor or coprocessor encounters an instruction that cannot be processed, an undefined instruction exception is generated. This exception mechanism can be used for software simulation. c. Software interrupt: This exception is generated by executing the SWI instruction and can be used to call the privileged operation instruction in the user mode. This exception mechanism can be used to implement the operating system call function. d. Instruction prefetch abort: If the address of the processor prefetch instruction does not exist or the address does not allow access to the current instruction, the memory issues an abort signal to the processor, but the instruction prefetch occurs when the prefetched instruction is executed. Abort the exception. e. Data access abort: If the target address of the processor data access instruction does not exist, or the address does not allow access to the current instruction, the processor generates a data access abort exception. f. External interrupt request: When the ARM external interrupt request pin is valid and the I bit in the CPSR is 0, an IRQ exception is generated. The system's peripherals can interrupt the service through this exception request. g. Fast interrupt request: When the ARM fast interrupt request pin is valid and the F bit of the CPSR is 0, an FIQ exception is generated. D, ARM processor response process to abnormal interrupt a. Store the address of the next instruction in the corresponding connection register LR. b. Copy the CPSR to the corresponding SPSR. c. Forcibly set the operating mode bit of the CPSR according to the type of the exception. d. Force the PC to take an instruction execution from the associated exception vector address and jump to the corresponding exception handler. E, ARM processor returns from the exception interrupt handler a. Restore the processor state of the interrupted program and copy the SPSR to the CPSR. b. If the interrupt disable bit is set when entering the exception processing, clear it here. c. The value of the connection register LR is subtracted from the corresponding offset and sent to the PC. F, reset exception interrupt handler does not need to return. The execution of the entire user program begins at the reset exception interrupt routine. The utility model discloses an Electronic Cigarette with atomizer oil core separation structure, which comprises a atomizer assembly and a battery assembly; The utility model has the advantages of reasonable structure design and high practicability. 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