The PCI bus is a bus in which addresses and data are multiplexed, ie, addresses and data occupy the same set of signal lines AD. All signals of the PCI bus are synchronized with the clock signal, and all signal changes occur at the rising edge of the clock or at the rising edge of the clock. As shown in the figure below, in addition to the clock signal CLK and the data address multiplexing signal AD, the PCI bus should also include at least FRAME# (used to indicate the start of a data transfer), C/BE# (Command/Byte Enable), IRDY # (Initiator Ready for data), TRDY # (Target ready), DESEL # (Device Selec, chip select signal for selecting the PCI device) and GNT # (Grant) signals. Note: For the complete signal timing diagram, please refer to PCI Spec. The # after the signal name indicates that the signal is active low. A simple example is introduced below. The host receives data from a specific slave. On the first clock rising edge, FRAME# and IRDY# are both inactive indicating that the bus is currently idle. At the same time, the GNT# signal of a device is active, indicating that the bus master has selected the current device as the next initiator (can be understood as the host). On the second clock rising edge, FRAME# is pulled down by the initiator, indicating that the new transaction has started. At the same time, addresses and commands are sent to the AD in turn, and all other devices (slaves) on the bus latch this information and check if the address and command match themselves. On the third clock rising edge, IRDY# is active, indicating that the host is ready to receive data. The rotated arrow on the AD signal indicates that the AD signal is currently in a tri-state (in the output and input transition state), ie, the Turn-around cycle. It should be noted that the TRDY# should be in the inactive state at this time to ensure smooth execution of the Turn-around cycle. On the fourth rising edge of the clock, a slave on the PCI bus confirms the identity, and in turn pulls down the DEVSEL# signal and TRDY# and outputs the corresponding data to the AD. At this point, the FRAME# signal is active, indicating that this is not the last data. On the fifth clock rising edge, TRDY# is inactive, indicating that the slave is not yet ready, so all operations are suspended for one clock cycle (or a Wait State is inserted). The PCI bus allows up to 8 such Wait States. On the sixth clock rising edge, the slave sends the second data to the master. At this point, the FRAME# signal remains active, indicating that this is not the last data. On the seventh clock rising edge, IRDY# is inactive, indicating that the host is not yet ready to insert a Wait State again. However, the slave can still send data to the AD. On the rising edge of the eighth clock, the third data on the AD is sent to the host. Since the FRAME# signal is pulled high, that is, inactive, it indicates that this is the last data of this transaction. After this, all the control signals are pulled high and are in the inactive state. AD, FRAME#, and C/BE# are in tristate. Signal timing Wired Earphones,Waterproof Earbuds,Noise Cancelling Earphones,Gaming Earphones GUANGZHOU LIWEI ELECTRONICS CO.,LTD , https://www.gdliwei.com