In high performance applications, such as communications, wireless infrastructure, the server, as well as broadcast video test and measurement device, when the system needs to integrate more functions and improved performance levels, it becomes increasingly complex hardware design, providing a reference sequence for the system The board-level clock tree is also moving toward this trend. In the design of the clock tree, the “ unchanged ” strategy does not apply. Optimizing the clock tree to meet performance and cost requirements depends on many factors, including system architecture, integrated circuit ( IC ) timing requirements (frequency, signal format, etc.). And jitter requirements for end applications.

Reference Timing - When to Use Crystal or Clock

The first design principle is to clarify the reference clock requirements for hardware design and select the reference clock types for the processors, FPGAs , ASICs , PHYs , DSPs, and other components in the system. If the IC has an integrated oscillator and an on-chip phase-locked loop ( PLL ) for on-chip timing , a quartz crystal can usually be used. Quartz cost effective, because of its excellent phase noise characteristics are widely used, they are placed close to the IC to simplify the circuit board layout. One of the disadvantages of crystals, however, is that the frequency varies significantly over the entire temperature range, exceeding the stability requirements of high precision ppm levels in many serializer / serializer ( SerDes ) applications . In many high-speed SerDes applications that require high stability , a crystal oscillator ( XO ) is recommended because it ensures more reliable stability than passive crystals.

When multiple reference frequencies are required, a clock generator and a clock buffer are typically used. In some applications, the FPGA/ASIC has multiple clock domains for the data path, control plane, and memory controller interface, requiring multiple specific reference frequencies. Clock generators and buffers are also preferred if the IC does not provide a crystal input interface , or when the IC needs to be synchronized with an external reference (synchronous source application), or when the desired high frequency reference is difficult to generate from the crystal.

Free running contrast synchronous clock tree

Once the hardware design is determined and the crystal is selected for some of the devices, the next step is to choose the timing architecture for the remaining clocks: free running or synchronization. For applications that require one or more separate reference clocks, and a phase locked loop with no special requirements or for synchronization, the XO, a clock generator and a clock buffer is ideal. Processors, memory controllers, SoCs, and peripheral components (for example, USB and PCI Express converters) typically use a combination of XO , clock generator, and clock buffers to provide reference timing for free-running and asynchronous applications.

If an application requires one or two timing sources, XO is the best choice; clock generators and buffers are better suited for applications that require multiple independent clocks at the same time. The clock generator is capable of synthesizing multiple clocks of different frequencies, but sacrificing partial jitter performance compared to a clock tree consisting of a clock buffer plus XO . The clock buffer can be combined with the XO reference to allocate multiple clocks of the same frequency and achieve the lowest jitter for the multi-output clock tree.