Here are some experiences to share with you. I hope that I can help some newcomers to IC design, so that they can take less detours! There are many different areas in the IC industry, and the characteristics of IC designers will be somewhat different. A good IC designer in the A field may take a long time to become familiar with the knowledge of the B field. At the beginning of our career, we should ask ourselves some questions, what kind of IC designers do we want to be? consumption? PC peripheral? Communication? Microprocessor or DSP? and many more. The basic rules and procedures of IC design are the same, no matter what kind of thing will be added to it. HDL, FPGA and software are the best tools to help us understand the chip. The soul of IC is knowledge. So the first challenge we will encounter will be to get information about the design, then understand the information and apply it. But some information is not free, we need to join some associations or buy some documents from organizations such as IEEE/ISO. Designers should have a strong background to quickly understand them and even improve the standards that exist. A good designer should have sufficient design skills and tools to apply knowledge and accumulate them. E.g: 8-port Ethernet conversion HUB controller Knowledge required: IEEE 802.3 standard, including 10 MHz Ethernet and 100 MHz Fast Ethernet. Related fields: Asynchronous Transfer Mode (ATM), IEEE 802.11 Infinite LAN, IEEE 1394, USB, etc. HDL, computer simulation and digital parts that only address the ASIC design flow. If there is any analog part in the IC, he will either rely on the analog designer or buy from another manufacturer. Even some pure digital parts can be purchased from other manufacturers to speed time to market. Those parts that are not designed by us are called IP, including HDL code, netlist, and hard core. The technology we design depends on the hard core. Some IPs are very expensive, such as the PHY in USB 2.0. Some small companies don't have enough manpower and software resources to do some work, and even they can't order enough crystals during the out-of-stock period, so service companies have replaced their jobs. But not every IP meets our needs, sometimes we need to make some changes after the purchase. We have to decide which IPs to use before designing. At the beginning of the design, the designer must understand all relevant standards, specifications, and algorithms. But there are many ways to apply these specifications and algorithms. The best structure is a combination of fast and minimal chip size. Unfortunately, fast demands are often opposed to the need for minimum chip size. Therefore, planning an optimal structure before HDL coding works is also an important issue. E.g: 1: divider The divisor is fixed. The quickest way is to look up the table, but this method requires a lot of memory. We can continue to subtract the number from the dividend until the new dividend is smaller than the divisor. It will take more time but with minimal hardware. There are many ways to build dividers, each with its own advantages and disadvantages. 2: Dynamic evaluator for image processing The most similar 8&TImes;8 module was found in the previous picture, throughout the movie clip. The most basic method is full search and three-step search. Many papers have discussed the structure of optimizing hardware complexity and speed, which I will not explain here. A good designer should be trained and continually experienced. We have to be very careful and patient in every design work. Because an NRE will consume a lot of money and weeks, if he accidentally makes a mistake, the designer will be responsible for money and plan failure. Experience and caution may be the best way to complete a successful design project. The following terms are some suggestions for a steady and successful design: (Some of my friends may have pointed out some of them, I will only give a brief description here, which may be slightly different) Naming style: 1. Do not use keywords to make signal names; 2, do not use the VERILOG keyword to do the signal name; 3. The meaning of the named signal; 4. Name the I/O port with the shortest name possible; 5. Do not mix signals with high and low conditions; 6, the first letter of the signal must be AZ is a rule; 7. Make the module name, instance name, and file name the same. Coding style: Remember, a good code is easy for others to read and understand. 1. Add as many explanatory statements as possible; 2. Fix the encoding format and unify all modules in one design, rooted from the format defined by the project leader; 3. Divide all designs into different numbers of different modules or entities; 4. All signals in an always/process must be relevant; 5. Don't use keywords or some grammar that is often used for security synthesis; 6, do not use complex logic; 7. All conditions in an if statement must be relevant; design style 1. It is strongly recommended to use synchronous design; 2. Always remember timing issues during design; 3. At the beginning of a design, consider the ground level or high level reset, synchronous or asynchronous reset, rising edge or falling edge triggering, etc., and comply with it in all modules; 4. Use if and case in different situations; 5. Be careful when latching a signal or bus; 6. Make sure that the output signals of all registers can be reset/set; 7. Never read any internal memory (such as SRAM) before writing. 8. Data buffering when transferring data from one clock to another. He works like a dual clock FIFO; 9. Two-dimensional arrays can be used in VHDL, which is very useful. In VERILOG he can only be used in the test module and cannot be integrated; 10. Follow the register-inregister-out rules; 11. The comprehensive tool for synopsys DC is very stable, and no bugs will be generated from the synthesis tool; 12. Make sure that the FPGA version is as similar as possible to the ASIC version, especially the SRAM type. If the version is consistent, it is ideal. 13. Use BIST in embedded memory; 14, virtual cells and some correction circuits are required; 15, some simple test circuits are also needed, often in a chip there are many test modules; 16, do not use a gated clock unless low power consumption; 17. Don't rely on scripts to ensure design. But some good constraints in the script can perform better (such as forward adders); 18, if the time is sufficient, replace the MUX with a multi-latch by the clock; 19. Do not use an internal tri-state. The ASIC requires a bus keeper to handle the internal tri-state. 20. Make padinserTIon in toplevel; 21, be careful when choosing a pad (such as pull ability, Schmitt trigger, 5 volts withstand voltage, etc.); 22. Be careful of problems caused by clock skew; 23. Do not try to generate a half-cycle signal; 24, if there are many functions to be corrected, please do it one by one, fix a function to check a function; 25. It is a good practice to arrange the number of bits per signal in a computational equation, even if the synthesis tool can do it; 26. Do not use the divider provided by HDL; 27. Cut unnecessary clocks. It can cause a lot of trouble in design and layout, most FPGAs have 1-4 dedicated clock channels; These are the best points that everyone can follow in design, which can make your design better.
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