0 Preface In the process of modern navigation computer systems toward miniaturization, navigation computer systems using high-performance digital signal processors and programmable logic devices have high performance advantages. In the embedded micro-navigation computer system based on floating-point DSP and complex programmable logic device (CPLD) structure developed by our research group, DSP is responsible for navigation solution task, and CPLD is used to assist DSP to control peripheral communication interface chip. To reduce the control tasks of the DSP, to make it more focused on the solution of the navigation task. CPLD can improve the flexibility of navigation computer control and configuration, facilitate system upgrade and update, make interface configuration more flexible, suitable for different sensors and easy to apply to integrated navigation system using multi-sensor information fusion, give full play to DSP Computing power to improve navigation performance. The CPLD in this embedded navigation computer system uses Xilinx's XC95144, which supports in-system programming (InSystemProgramming) and the extended IEEEStd1149.1JTAG boundary-scan test specification. As a test specification, the JTAG standard has been adopted by most programmable logic devices. The general programming method for the chip is to transfer the parallel port of the PC to its JTAG port through the download cable provided by Xilinx, and use the PC to download software to implement software update. Due to the signal characteristics of the JTAG port, the download cable should not be too long, otherwise the signal will be distorted. In addition, if the software needs to be updated and upgraded after the system is put into use, the cable must be opened by the cable. Facilitate maintenance and update of the system. Based on the research of JTAG interface characteristics, this paper proposes a software update program using UART serial communication, and implements software update for CPLD devices based on DSP interface control, so that PLD devices programmed with JTAG port can realize remote Updates and upgrades. 1JTAG interface principle JTAG is a test standard proposed by the IEEE Joint Test Action Group (JointTestAcTIonGroup), which was originally designed to address test issues due to increased chip integration and board-level device density. This standard has now been adopted by most device vendors and designed into chip circuits to support its device in system debug or programming functions. For the CPLD device used in this paper, the structure of the JTAG interface is shown in Figure 1. The JTAG standard defines four basic units: Test Access Port TAP (TestAccessPort), Data Register, Instruction Register, and TAP Controller. The TAP port contains four JTAG signals: test clock input pin TCK, test data input pin TDI, test data output pin TDO, and test mode select pin TMS. The data register mainly includes two kinds: BYPASS register and BSR (BotlndaryScanRegister) register. The BSR is formed by BSC (BotmdaryScanCell) in series. It is through the BSC scan chain circuit that the CPLD configuration information from the TDI can be moved into the chip. Thereby the function of erasing and programming the device is realized. The TAP controller is actually a state machine with 16 states that controls the test access, instruction registers, and data registers. The TAP controller state transition diagram is shown in Figure 2. The state of the TAP controller is controlled by two signals, TMS and TCK. When the data on the TDI needs to be moved into the instruction register, the TAP controller can be put into the Shift-IR state; when the data on the TDI needs to be moved to the data register, it can be put into the Shift-DR state. Through the state transition of the TAP controller, the configuration information of the CPLD can be moved into its internal logic. In the PC-based programming method, the configuration information file of the CPLD is stored in the PC, and the download software running in the PC continuously reads the configuration information of the device, and simulates the timing and logic of the JTAG test port through its parallel interface, thereby realizing its Software updates and downloads. This article will use the DSP in the navigation computer system to implement this programming method: the configuration file of the CPLD is sent to the navigation computer system through the UART serial port of the DSP, and then the DSP parses and executes the instructions in the configuration file, through the I/ of the DSP. The O port simulates the JTAG port signal behavior to implement the software update function of the CPLD device. Based on this scheme, it is possible to conveniently remotely program and update the CPLD using a common serial port. 　　
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