Embedded devices have become more and more widely used due to their hardware configuration and flexibility. Especially in the FPGA-based hardware system, there are many applications. Currently, many modules such as embedded network port, embedded PCI/PCI-E, and embedded USB are implemented in many products. However, there are still relatively few embedded devices implemented in DSP. Generally, DSPs directly integrate these device modules, and users select different types of DSP chips to meet product application requirements. But for some more special embedded devices, DSP can also achieve this function. TI's DSP chip C6727B, due to its on-chip integration of dMAX modules, makes it possible to implement embedded FIFOs. The essence of implementing the embedded FIFO is to set a piece of RAM space on the chip into a FIFO space. The data exchange between the FIFO and the external device is completed by the EMIF interface. The data read and write of the FIFO does not require the CPU of the DSP to participate, thereby improving the performance of the entire system and achieving data exchange and data processing simultaneously. This article takes the data transmission of dMAX and EMIF interface as an example to introduce the design, configuration and use of embedded FIFO. dMAX and its structure dMAX (DualDataMovementAccelerator) is an on-chip device unique to TI's DSP chip C6727B. Data transfer between on-chip RAM, on-chip and off-chip devices, and two off-chip devices can be implemented using dMAX and EMIF (External Memory Interface). dMAX is mainly composed of an event and interrupt processing module, an event encoder, a transmission event module, and the like. The event module is divided into two high-priority and low-priority modules, each with independent event entry and event parameter tables, and a separate interface with the CPU. This allows dMAX to handle two different events simultaneously. When accessing the CPU port, MAX0 has a higher priority and MAX1 has a lower priority. dMAX is capable of performing advanced 1D, 2D, and 3D data memory transfers, allowing DSPs to focus on signal processing tasks and significantly improve system performance. Suitable for sub-frame extraction of images or sub-channel extraction of speech signals. The data exchange center inside the DSP can realize data exchange between on-chip RAM, EMIF and HPI interface under the control of dMAX. This article describes the data exchange between the on-chip RAM and the EMIF interface under dMAX control. If the DSP uses the normal asynchronous interface mode, the data transmission needs to be established, strobed and maintained in three stages, and at least five EMIF clocks are required (one clock is established and maintained, and three clocks are strobed). In order to ensure the reliability of communication, 10 EMIF clocks are generally used (establish 3 clocks, keep 2 clocks, and strobe 5 clocks). The EMIF clock is as fast as 133MHz; thus, the communication rate using the asynchronous interface is generally 13.3M & TImes; 32b / s (using a 32-bit data bus width). In addition, asynchronous interface data transfer must use instructions to achieve data movement with the participation of the CPU. Will consume a lot of CPU overhead, in many high-speed data acquisition and processing, will reduce the overall performance of the system. To this end, dMAX is used to realize embedded FIFO data transmission to overcome the shortcomings of asynchronous transmission. The transmission adopts burst read and write mode, which can continuously read and write 8 data. A total of only 20 clocks is needed, and the communication rate is increased to 53.2M & TImes. ; 32b / s, increase the read / write rate of 4 times. It can also be run in the background with DMA, which will greatly reduce the overhead of reading and writing data of the entire system, thus enabling more complex and reliable algorithm processing. Embedded FIFO design The design of the embedded FIFO is mainly to control the seven parameters of the FIFO. These seven parameters are base address, space size, empty flag, full flag, error flag, read pointer and write pointer. The base address and space size are used to plan a memory space that is used by the FIFO device and protected by the FIFO device so that other devices and programs cannot access the space. In order to facilitate the operation, the space size is generally an integer power of 2, but is not required. Specific to the C6727B model DSP, the maximum size of the space is 1M elements, the element size can be 8 bits, 16 bits or 32 bits of data, can not be other types of data. The base address can be any address of the memory space, and is also a boundary point of space size for convenience of operation. For example, the FIFO of an 8-element has a base address of XXXXX000b, that is, the lower 3 bits of the address are 0, and the base address is definitely an integer number of 8. Similarly, a 64-element FIFO has a lower 6 bits of 0. The special requirements of the base address and space size avoid the problem that the address at the time of access spans multiple pages, and the access speed of the FIFO can be improved. The empty flag and the full flag are used to indicate the storage state of the FIFO. The read pointer and write pointer are used to indicate the current address of the read and write. The error flag indicates an erroneous operation on the FIFO. When the FIFO is still written while the FIFO is full, or the FIFO is still reading the FIFO, the FIFO will terminate the current operation and set the error flag. The FIFO write operation has only one way of working, that is, each time a new data is written, the write pointer is incremented by one until it is full. The FIFO read operation has two modes of operation, namely standard operation and Multi-tap Delay Transfer operation. Standard operations are the same as write operations. Multi-order delay operation is generally used for filtering processing. When it is necessary to filter the input signal, each time you want to read the data of a window from the FIFO and perform filtering processing, the data window still only moves one data. In the case of standard operation, if the data of a window is read, the FIFO will pop all the data of the window. Multi-level delay operations only pop up one data. This method of operation is very suitable for smoothing, FIR and other filtering of voice or AD sample data. It should be noted that the data window size of the multi-level delay operation needs to be set. If the number of data stored in the FIFO is smaller than the data window, the FIFO terminates the current operation and gives an error flag. System hardware structure The C6727B has a big difference with other DSPs. The C6727B no longer provides a dedicated external interrupt pin. Instead, it uses the GPIO pin in conjunction with dMAX to configure the GPIO pin as an external interrupt pin through register settings. In order to realize the real-time operation of the FIFO, once the peripheral writes data to the FIFO, it sends an interrupt signal to the CPU of the DSP to notify the CPU to read the data. To do this, you need to use an external interrupt pin to configure the AXR[8] of the C6727B's audio serial port as a general-purpose GPIO pin and set it as an interrupt pin in dMAX. In this case, you need to set the CONFIGMACSP0 register of the audio serial port to 0x0001, as shown in Figure 3. At this point, the audio serial port can no longer be used as an ordinary audio port, but is configured as an IO interface. After the audio serial port is configured, once the AXR[8] pin has a rising edge, McASP0 activates event 36 of dMAX and sends an internal interrupt 13 to the CPU. McASP's interrupt-related register configuration is the focus of the above solution. It is configured as a general-purpose IO pin using the PFUNC register; the PDIR register controls the direction of the IO pin; if it is an output pin, it is output high and low by the POUT pin. If it is an input pin, the reference is read by the PDIN register. The state of the pin; in addition, the PDCLR and PSET registers can be used to clear or set the state of the output pins. System software design The system software design mainly includes the initialization of McASP, the initialization of dMAX, the initialization of FIFO, and the interrupt enable. The main program of the system only needs to wait for the interrupt to perform corresponding processing. The main data transmission work is done automatically by dMAX according to the software configuration, and no CPU is required to participate. Figure 4 shows the flow of implementing the FIFO write by the peripheral and the DSP reading the FIFO data. The dotted line in the figure indicates the work done independently by dMAX, and the solid line portion indicates the work done by the CPU. The state exchanges between the two through internal interrupts. In order to improve the read/write rate of the FIFO, the burst mode is generally used for reading and writing. The read timing of the burst mode is shown in Figure 5. The write timing is similar to the read timing. The burst mode can only read and write 8 data at a time, and can also read and write 4 or 2 data at a time. The data setup and hold time during burst read and write can be set to at least 1 clock cycle, as shown in the figure. However, in order to communicate reliably, two clock cycles are generally used. The biggest saving time of the burst mode is that the continuous other data will no longer need to establish and maintain the cycle, but directly read and write, generally only need two clock cycles to complete a data read and write. In the fastest case, it takes only 20 clock cycles to read and write 8 data, and the read/write rate reaches 53.2M×32b/s, which meets the requirements of most devices. to sum up The unique structure of dMAX makes it possible to implement embedded FIFOs. This paper introduces the basic structure of dMAX based on C6727B and the embedded FIFO software and hardware design based on dMAX. The general GPIO pin is set as the interrupt. In order to speed up the FIFO transmission rate, the burst read/write mode is used for data transmission. The implementation of the embedded FIFO makes the communication between the DSP and the external device more convenient and faster, and does not require the participation of the CPU, which reduces the burden on the CPU, and the CPU can focus on complex algorithm processing. What is an wall ap? In life, many times we will encounter a bad network situation, generally when the network is bad will affect everyone's mood, everyone likes the situation of network unobstructed, so will go to find a way to keep the network smooth, and wall ap can help you keep the network unobstructed, let's take a look. Wall Ap Wireless Ap,Wall Mount Access Point,Wall Mount Wifi Access Point,Access Point Ac In-Wall Shenzhen MovingComm Technology Co., Ltd. , https://www.szmovingcomm.com
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