CPU

The CPU is the core accessory in the computer. All operations in the computer are the CPU's responsibility to read the instructions, decode the instructions, and execute the core components of the instructions. Its function is mainly to interpret computer instructions and process data in computer software.

Central Processing Unit - Basic Introduction The Central Processing Unit (CPU) is one of the main equipments of electronic computers. Its function is mainly to interpret computer instructions and process data in computer software. The so-called computer programmability mainly refers to the programming of the CPU. The CPU, internal memory, and input/output devices are the three core components of modern computers. The CPU manufactured by (zh-hans: integrated circuit; zh-hant: integrated circuit), before the 1970s, originally consisted of several independent units, and later developed a microprocessor to make the complicated circuit of the CPU possible. A single tiny powerful unit.

The name "central processing unit" is a description of a series of logical machines that can perform complex - (zh-hans: computer programs; zh-hant: computer programs). This vague definition makes it easy to include early computers before the name "CPU" was used universally. In any case, at least since the early 1960s, this name and its abbreviation have begun to be widely used in the computer industry. Although the "central processing unit" has undergone dramatic development in terms of physical form, design and manufacturing, and execution of specific tasks compared to the early days, its basic operating principle has not changed.

Early CPUs were usually ordered for large-scale, application-specific computers. However, this method of customizing the CPU for a particular application has largely made it possible to develop a processor class that is cheap, standardized, and suitable for one or more purposes. This standardized trend began in the mainframe and microcomputer era consisting of a single transistor and accelerated with the advent of integrated circuits. ICs enable more complex CPUs to be designed and manufactured in a small space (in the order of microns). The standardization and miniaturization of the CPU all make this type of digital device (Hong Kong translating - electronic parts) appear far more frequently in modern life than computers with limited applications. Modern microprocessors are found in various items ranging from cars to mobile phones to children's toys.

Central Processing Unit - Composition The central processing unit CPU includes an arithmetic logic unit, a register unit, and a control unit. The central processor fetches instructions from memory or cache memory, places them in instruction registers, and decodes the instructions. It decomposes the instruction into a series of micro-operations, then issues various control commands and executes the micro-operation sequence to complete the execution of one instruction. An instruction is a basic command that the computer specifies the type of operation to perform and the operands.

1 arithmetic logic unit. You can perform fixed-point or floating-point arithmetic operations, shift operations, and logical operations, as well as address operations and conversions.

2 register parts. Includes general registers, special registers, and control registers. General-purpose registers can be divided into fixed-point and floating-point numbers, which are used to store register operands and operation results in instructions. General purpose registers are an important part of the central processor and most instructions have access to general purpose registers.

3 control parts. It is mainly responsible for decoding the instruction and issuing control signals for each operation to be performed for completing each instruction. There are two kinds of structure: one is the micro-program control method based on micro-storage; the other is the control method based on the logic hard-wiring structure.

Central Processing Unit - Operational Principles The main operating principle of the CPU, regardless of its appearance, is to execute a series of instructions stored in what is called a program. Discussed here is a device that follows the general-(zh-hans: von Neumann; zh-hant: von Neumann)-architecture design. The program is stored in computer memory as a series of numbers. Almost all - (zh-hans: von Neumann; zh-hant: von Newman) - The operating principle of the CPU can be divided into four stages: fetch, decode, execute, and Writeback.

The first stage, extracting, retrieves instructions from the program memory (as numerical values ​​or as a series of values). The program memory (PC) specifies the location of the program memory and the program counter stores the value for identifying the current program location. In other words, the program counter records the traces of the CPU in the current program. After the instruction is fetched, the PC increases the memory unit according to the instruction length. The fetching of instructions often must be looked for from relatively slow memory, resulting in the CPU waiting for instructions to be delivered. This problem is mainly addressed in the cache and pipeline architecture of modern processors (see below).

The CPU determines its execution behavior based on the instructions extracted from the memory. In the decoding phase, the instructions are disassembled into meaningful pieces. The values ​​are interpreted as instructions according to the CPU's instruction set architecture (ISA) definition. Some of the instruction values ​​are opcodes, which indicate which operations are to be performed. Other values ​​usually provide information necessary for the instruction, such as the operation target of an addition operation. Such an operation target may provide a constant value (ie, an immediate value) or a spatial address value: a register or a memory address, which is determined by the addressing mode. In the old design, the instruction decoding part of the CPU is a hardware device that cannot be changed. However, in many abstract and complex CPUs and ISAs, a microprogram is often used to help convert instructions into various forms of signals. These microprograms can often be rewritten in finished CPUs, making it easy to change the decoding instructions.

After the extraction and decoding stages, it then proceeds to the execution stage. In this phase, connect to various CPU components that can perform the required calculations. For example, an addition operation is required, and an arithmetic logic unit (ALU) will be connected to a group of inputs and a group of outputs. The input provides the value to be added, and the output will contain the sum result. The ALU includes circuitry to perform simple general operations and logic operations (such as addition and bit operations) at the output. If the addition produces a result that is too large for the CPU, the arithmetic overflow flag may be set in the flags register (see the following discussion of numerical precision).

In the final stage, write back and simply write back the results of the execution phase in a certain format. The result of the operation is very often written into the scratchpad inside the CPU for quick access by subsequent instructions. In other cases, the result of the calculation may be written into a slower, but larger, and cheaper main memory. Some types of instructions operate program counters without directly producing result data. These are generally called "jumps" and bring loop behavior, conditional execution (through conditional jumps), and functions in the program. Many instructions also change the status bits of the flags register. These flags can be used to influence program behavior because they often show various results of operations. For example, a "comparison" instruction determines the size of two values ​​and sets a value on the flag register based on the comparison result. This flag can be determined by the following jump instruction.

After the instruction is executed and the result data is written back, the value of the program counter is incremented, the entire process is repeated, and the next instruction cycle normally extracts the next sequential instruction. If the jump instruction is completed, the program counter will be modified to the jumped instruction address, and the program will continue to execute normally. Many complex CPUs can extract multiple instructions at a time, decode them, and execute them at the same time. This section generally refers to "classic RISC pipelines", which are actually rapidly popularized in a large number of electronic devices using simple CPUs (often referred to as micro-controllers).

CPU - Performance Indicators CPU's main performance indicators are:

The main frequency is also called the clock frequency, and the unit is MHz, which is used to indicate the speed of the CPU. CPU's main frequency = FSB × multiplier. Many people think that the main frequency determines the speed of the CPU, which is not only one-sided, but also for the server, this awareness has also shown a deviation. So far, there is no definite formula to achieve the numerical relationship between the main frequency and the actual operation speed. Even the two major processor manufacturers, Intel and AMD, are still controversial at this point. We are from Intel. The development trend of the products can be seen that Intel pays great attention to strengthening the development of its own frequency. Like other processor manufacturers, some people once took a 1G Quanta to compare, and its operating efficiency is equivalent to 2G Intel processors. Therefore, the frequency of the CPU is not directly related to the actual computing power of the CPU, and the main frequency indicates the speed of the digital pulse signal oscillation in the CPU. In Intel's processor products, we can also see such an example: The 1 GHz Itanium chip can perform almost as fast as the 2.66 GHz Xeon/Opteron, or 1.5 GHz Itanium 2 is about as fast as the 4 GHz Xeon/Opteron. The computing speed of the CPU depends on the performance of various aspects of the CPU's pipeline. Of course, the clock speed is related to the actual operation speed. It can only be said that the clock speed is only one aspect of the performance of the CPU and does not represent the overall performance of the CPU.

The FSB FSB is the reference frequency of the CPU and the unit is also MHz. The CPU's FSB determines the speed of the entire motherboard. To put it plainly, in the desktop, we are talking about overclocking, all of which are FSBs (of course, under normal circumstances, the CPU multiplier is locked) believe this is well understood. But for the server CPU, overclocking is absolutely not allowed. As mentioned before, the CPU determines the running speed of the mainboard. The two are running synchronously. If the server CPU is overclocked and the FSB is changed, asynchronous operation will occur. (A lot of motherboards in the desktop support asynchronous operation.) This will cause the entire server. System instability. In most computer systems, the FSB is also the speed of synchronous operation between the memory and the motherboard. In this way, it can be understood that the FSB of the CPU is directly connected with the memory to achieve synchronous operation between the two. The FSB and FSB frequencies can easily be confused. The following front-side bus introduces us to the difference between the two.

Front Side Bus (FSB) Frequency The Front Side Bus (FSB) frequency (ie, bus frequency) directly affects the speed of direct data exchange between the CPU and memory. There is a formula that can be calculated, that is, data bandwidth = (bus frequency × data bit width)/8. The maximum data transmission bandwidth depends on the width and transmission frequency of all simultaneously transmitted data. For example, the Xeon Xeon, now supporting 64-bit Xeon, has a front-side bus of 800MHz. According to the formula, its maximum data transfer bandwidth is 6.4GB/sec. The difference between the FSB frequency and the FSB: The speed of the FSB is the speed of data transmission, and the FSB is the speed of synchronous operation between the CPU and the motherboard. In other words, the 100MHz FSB specifically refers to the digital pulse signal oscillating 10 million times per second; and the 100MHz FSB refers to the amount of data that the CPU can accept per second is 100MHz × 64bit ÷ 8bit / Byte = 800MB / s. Its realization in the "HyperTransport" framework, so that the actual sense of the front-side bus (FSB) frequency has changed. Before we know that IA-32 architecture must have three important components: memory controller Hub (MCH), I / O controller Hub and PCI Hub, like Intel's typical chipset Intel 7501, Intel 7505 chipset, dual-Xeon Processors are tailor-made, they include the MCH for the CPU provides a front-side bus with a frequency of 533MHz, with DDR memory, the front-side bus bandwidth can reach 4.3GB / sec. However, as processor performance continues to increase, it has brought many problems to the system architecture. The "HyperTransport" architecture not only solves the problem, but also increases bus bandwidth more effectively. For example, the AMD Opteron processor and the flexible HyperTransport I/O bus architecture allow it to integrate a memory controller so that the processor does not pass the system bus. Data is exchanged directly with memory to the chipset. In this case, the front-side bus (FSB) frequency in the AMD Opteron processor does not know where to start.

Bits and word lengths of the CPU: Binary is used in digital circuits and computer technology. The codes are only "0" and "1". No matter whether "0" or "1" is a "bit" in the CPU. Word length: The number of digits in a computer technology that can be processed once by the CPU in a unit of time (at the same time). So a CPU that can handle 8-bit data is usually called an 8-bit CPU. Similarly, the 32-bit CPU can process 32-bit binary data in unit time. The difference between byte and word length: Since commonly used English characters can be represented by 8-bit binary, 8 bits are usually referred to as one byte. The length of the word length is not fixed, and it is different for different CPUs and word lengths. An 8-bit CPU can only process one byte at a time, while a 32-bit CPU can process 4 bytes at a time, and a 64-bit CPU can handle 8 bytes at a time.

The frequency multiplier coefficient is the relative ratio between the CPU main frequency and the FSB. At the same FSB, the higher the multiplier, the higher the CPU frequency. But in fact, under the premise of the same FSB, the CPU of high frequency multiplication itself is not significant. This is because the data transfer speed between the CPU and the system is limited, and the CPU that seeks high frequency multiplication to get a high frequency will have a clear "bottleneck" effect. The CPU's limit speed from the system can't satisfy the CPU operation. speed. In addition to the engineering version of Intel's CPU is locked frequency multiplier, and AMD did not lock before.

Cache cache size is also one of the important indicators of the CPU, and the structure and size of the cache have a great influence on the CPU speed. The cache frequency in the CPU is extremely high, which is usually the same frequency as the processor, and the working efficiency is far greater than the system memory. And hard drive. In actual work, CPUs often need to repeatedly read the same data blocks, and the increase in cache capacity can greatly increase the hit rate of the CPU's internal read data, instead of searching for memory or hard disk, in order to improve system performance. . However, due to factors such as CPU chip area and cost, the cache is very small. L1 Cache (level 1 cache) is the first level of CPU cache, divided into data cache and instruction cache. The capacity and structure of the built-in L1 cache have a great influence on the performance of the CPU. However, the cache memory is composed of static RAM, and the structure is relatively complex. In the case where the CPU die area cannot be too large, the capacity of the L1 cache is not It may be too big. The L1 cache of a typical server CPU is usually 32-256 KB.

L2Cache (secondary cache) is the second level of CPU cache, divided into internal and external chips. The internal chip L2 cache runs at the same speed as the main clock, while the external L2 cache only has half the main clock. L2 cache capacity will also affect the performance of the CPU, the principle is bigger, the better, now the largest home CPU capacity is 512KB, and the L2 cache CPU and server workstations up to 256KB-1MB, some up to 2MB or 3MB .

L3Cache (three-level cache) is divided into two types. The early ones are external ones. Now they are all built-in. Its practical role is that the application of L3 cache can further reduce the memory delay, while improving the performance of the processor when calculating large amounts of data. Reducing memory latency and boosting the amount of computing power of large amounts of data are very helpful for games. Increasing the L3 cache in the server area still has a significant improvement in performance. For example, a configuration with a larger L3 cache makes more efficient use of physical memory, so its slower disk I/O subsystem can handle more data requests. Processors with larger L3 caches provide more efficient file system caching behavior and shorter message and processor queue lengths. In fact, the earliest L3 cache was applied to the K6-III processor released by AMD. At that time, the L3 cache was confined to the manufacturing process and was not integrated into the chip but was integrated on the motherboard. The L3 cache that can only synchronize with the system bus frequency is not much worse than the main memory. Later on the L3 cache was Intel's Itanium processor for the server market. Followed by P4EE and Xeon MP. Intel also plans to introduce a Itanium2 processor with 9MB L3 cache and dual-core Itanium2 processor with 24MB L3 cache. But basically L3 cache is not very important for processor performance improvement. For example, a Xeon MP processor with 1MB L3 cache is still not Opteron's opponent. This shows that the increase in front-side bus is more effective than the increase in cache. Improve performance.

Central Processing Unit - Extended Instruction CPU relies on instructions to calculate and control the system. Each CPU specifies a series of instruction systems that are compatible with its hardware circuitry at design time. The strength of the instruction is also an important indicator of the CPU. The instruction set is one of the most effective tools to improve the efficiency of the microprocessor. From the mainstream architecture of the current stage, the instruction set can be divided into two parts: a complex instruction set and a reduced instruction set. In terms of specific applications, such as Intel's MMX (Multi Media Extended), SSE, and SSE2 (Streaming-Single instruction multiple data) -Extensions 2), SSE3 and AMD's 3DNow! are all CPU's extended instruction sets, which enhance the CPU's multimedia, graphics, and Internet processing power. We usually refer to the CPU's extended instruction set as the "CPU instruction set." The SSE3 instruction set is also the smallest instruction set. Previously MMX contained 57 commands, SSE contained 50 commands, SSE2 contained 144 commands, and SSE3 contained 13 commands. Currently SSE3 is also the most advanced instruction set. The Intel Prescott processor already supports the SSE3 instruction set. AMD will add support for the SSE3 instruction set in future dual-core processors, and Transmeta's processors will also support this instruction set. CPU core and I/O working voltage, start from 586CPU, the working voltage of CPU is divided into two kinds of kernel voltage and I/O voltage, usually the core voltage of CPU is less than or equal to I/O voltage. The size of the core voltage is determined according to the production process of the CPU. Generally, the smaller the manufacturing process is, the lower the core operating voltage is; the I/O voltage is generally 1.6~5V. Low voltage can solve the problem of excessive power consumption and excessive heat.

The micron of the CPU manufacturing process manufacturing process refers to the distance between the circuit and the circuit within the IC. The trend in the manufacturing process is to develop the higher concentration. The more dense the IC circuit design, it means that in the same size area of ​​the IC, you can have a higher density, more complex circuit design. The main 180nm, 130nm, 90nm, and 65nm are now available. Intel Corporation also released a 45nm manufacturing process on November 16, 2007.

CPU instruction set (1) CISC instruction set CISC instruction set, also called complex instruction set, English name is CISC, (abbreviation of Complex Instruction Set Computer). In the CISC microprocessor, the various instructions of the program are executed serially in sequence, and the individual operations in each instruction are also performed serially in sequence. The advantage of sequential execution is that the control is simple, but the utilization of various parts of the computer is not high, and the execution speed is slow. In fact, it is Intel's x86 series (aka IA-32 architecture) CPU and its compatible CPUs, such as AMD, VIA. Even the new X86-64 (also known as AMD64) now belongs to the category of CISC. To know what an instruction set is, let's start with the CPUs of today's X86 architecture. The X86 instruction set was specifically developed by Intel for its first 16-bit CPU (i8086). The CPU-i8088 (i8086 simplified version) introduced by IBM in 1981 in the world's first PC was also using the X86 instructions, while the computer was The X87 chip was added to improve floating-point data processing capabilities, and the X86 instruction set and the X87 instruction set were collectively referred to as the X86 instruction set. Although with the continuous development of CPU technology, Intel has successively developed newer i80386, i80486 until the past PII Xeon, PIII Xeon, Pentium 3, and finally to today's Pentium 4 series, Xeon (excluding Xeon Nocona) However, in order to ensure that the computer can continue to run various applications developed in the past to protect and inherit rich software resources, all CPUs produced by Intel Corporation continue to use the X86 instruction set, so its CPU still belongs to the X86 series. Since the Intel X86 series and its compatible CPUs (such as the AMD Athlon MP) use the X86 instruction set, today's huge X86 series and compatible CPU lineup are formed. The x86 CPU currently has two types of intel server CPU and AMD server CPU.

(2) RISC instruction set RISC is an abbreviation of "Reduced Instruction Set Computing" in English, meaning "reduced instruction set." It was developed on the basis of the CISC command system. Some people test the CI C machine and showed that the frequency of use of various instructions is quite different. The most frequently used are relatively simple instructions, which only account for 20% of the total number of instructions. However, the frequency of occurrence in the program accounted for 80%. The complex instruction system will inevitably increase the complexity of the microprocessor, making the development time of the processor long and the cost high. And complex instructions require complex operations that inevitably slow down the computer. Based on the above reasons, the RISC-type CPU was born in the 1980s. Compared with the CISC-type CPU, the RISC-type CPU not only simplified the instruction system, but also adopted a so-called "superscalar and superpipelined structure", which greatly increased the parallel processing capability. . The RISC instruction set is the development direction of high performance CPU. It is opposite to the traditional CISC (complex instruction set). In contrast, RISC's instruction format is unified, the types are relatively few, and the addressing mode is also less than the complex instruction set. Of course, the processing speed increases a lot. At present, CPUs of this instruction system are commonly used in middle-to-high end servers, and particularly high-end servers all use CPUs of the RISC instruction system. RISC instruction system is more suitable for high-end server operating system UNIX, and now Linux also belongs to UNIX-like operating system. RISC-type CPUs are not compatible with Intel and AMD CPUs in software and hardware. At present, CPUs using RISC instructions in mid to high-end servers mainly include the following types: PowerPC processors, SPARC processors, PA-RISC processors, MIPS processors, and Alpha processors.

(3) IA-64

Whether or not EPIC (Explicitly Parallel Instruction Computers) is the successor of RISC and CISC systems has been a lot of controversy. In EPIC system alone, it is more like an important step of Intel's processor to RISC system. In theory, the EPIC system design CPU, in the same host configuration, deal with Windows application software is much better than Unix-based application software. Intel's server CPU with EPIC technology is Itanium Itanium (development codename Merced). It is a 64-bit processor and is the first in the IA-64 family. Microsoft has also developed an operating system codenamed Win64, which is supported on software. After Intel adopted the X86 instruction set, it turned to a more advanced 64-bit microprocessor. Intel did this because they wanted to get rid of the huge x86 architecture and introduce energetic and powerful instructions. As a result, the IA-64 architecture using the EPIC instruction set was born. In many ways, IA-64 has made significant progress over x86. It broke through many limitations of the traditional IA32 architecture and achieved a breakthrough in data processing capabilities, system stability, security, availability, and considerable rationality.

The biggest drawback of IA-64 microprocessors is that they lack compatibility with x86, and Intel can run two dynasty software better for IA-64 processors. It is on IA-64 processors (Itanium, Itanium 2... ) The x86-to-IA-64 decoder was introduced so that x86 instructions can be translated into IA-64 instructions. This decoder is not the most efficient decoder, nor is it the best way to run x86 code (the best way is to run x86 code directly on x86 processors), so Itanium and Itanium2 performance when running x86 applications Very bad. This has also become the root cause of X86-64.

(4) X86-64 (AMD64/EM64T)

AMD is designed to handle 64-bit integer arithmetic at the same time and is compatible with the X86-32 architecture. Which supports 64-bit logic addressing, while providing conversion to 32-bit addressing options; but the data manipulation instructions default to 32-bit and 8-bit, providing options for conversion to 64-bit and 16-bit; support for general purpose registers, if it is a 32-bit operation , it is necessary to expand the result into a full 64-bit. In this way, there are differences between “direct execution” and “conversion execution” in the instruction. The instruction field is 8-bit or 32-bit, which can avoid the field being too long. The generation of x86-64 (also called AMD64) is not groundless. The 32-bit addressing space of the x86 processor is limited to 4GB of memory, while the IA-64 processor is not compatible with x86. AMD fully considers the needs of customers and strengthens the functions of the x86 instruction set, so that this set of instructions can support 64-bit operation modes at the same time. Therefore, AMD calls their structures x86-64. Technically, AMD has introduced an R8-R15 general-purpose register as an extension of the original X86 processor registers in order to perform 64-bit operations in the x86-64 architecture, but in 32-bit environment, AMD is not completely Use these registers. The original registers such as EAX, EBX also expanded from 32-bit to 64-bit. Eight new registers have been added to the SSE unit to provide support for SSE2. The increase in the number of registers will bring about an increase in performance. At the same time, in order to support both 32- and 64-bit code and registers, the x86-64 architecture allows the processor to operate in two modes: Long Mode and Legacy Mode, and the Long mode is subdivided into two types. Mode (64bit mode and Compatibility mode compatibility mode). The standard has been introduced in the Opteron processor in the AMD server processor. This year also introduced support for 64-bit EM64T technology, before it was officially designated as EM64T IA32E, which is Intel's 64-bit extension technology name used to distinguish the X86 instruction set. Intel's EM64T supports 64-bit sub-mode, similar to AMD's X86-64 technology, using 64-bit linear plane addressing, adding eight new general-purpose registers (GPRs), and adding eight more registers to support SSE instructions. Similar to AMD, Intel's 64-bit technology will be compatible with IA32 and IA32E, and will only use IA32E when running a 64-bit operating system. The IA32E will consist of two sub-modes: a 64-bit sub-mode and a 32-bit sub-mode, which is backward compatible with AMD64. Intel's EM64T will be fully compatible with AMD's X86-64 technology. Now that the Nocona processor has added some 64-bit technology, Intel's Pentium 4E processor also supports 64-bit technology. It should be said that both are compatible with the 64-bit microprocessor architecture of the x86 instruction set, but there are some differences between the EM64T and the AMD64. The NX bits in the AMD64 processor will not be available on Intel processors.

CPU - Superpipeline & Superscalar Before understanding superpipeline and superscalar, first understand the pipeline. The assembly line is Intel's first use in the 486 chip. The assembly line works like an assembly line in industrial production. A command processing pipeline is composed of six different functional circuit units in the CPU, and then an X86 instruction is divided into five to six steps and then executed by these circuit units, so that one instruction can be completed in one CPU clock cycle. Therefore, the CPU speed is increased. Classic Pentium each integer pipeline is divided into four levels of water, that is instruction prefetch, decoding, execution, write back the results, floating point water is divided into eight levels of running water. Superscalar is the implementation of multiple processors at the same time through the built-in multiple pipelines, the essence of which is to exchange time for space. The super-pipelining is to complete one or more operations in a machine cycle by refining the flow of water and increasing the main frequency. The essence of this is to exchange space for time. For example Pentium 4's pipeline is up to 20 levels. The longer the step (level) of the pipeline design, the faster it can complete an instruction, so that it can adapt to higher CPU frequency. However, the long pipeline also brings certain side effects. It is very likely that the CPU with a higher clock speed will actually have a lower computing speed. Intel's Pentium 4 has this kind of situation, although its clock speed can be as high as 1.4G or more. , but its computing performance is far less than AMD 1.2G Athlon or Pentium III.