Application of TMS320C5402 in TV Digital Transmission Multiplexer

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Keywords: transport stream TMS320C5402 multiplexer

introduction

With the development of information technology, digital coding, digital storage, and digital processing of television signals have become more and more widespread. The newly developed digital limited television broadcasting system mainly includes an MPEG-2 encoder, a digital transmission multiplexer, a digital modulator, and a set top box. The multiplexer is an important part of the system, and the multiplexing of TS streams (Transport Stream) conforming to the MPEG-2 system layer standard ITU-TREC.H.222.1|ISO/IEC13818-1 is completed, and 64 QAM modulation is performed. Then, in order to transmit multiple digitized programs in a 6 MHx bandwidth. Considering the real-time processing, we use Texas Instruments' TMS320C5402 (C5402) DSP as the main control chip. This paper first introduces the structure of the TS stream, the composition of the C5402 chip and the multiplexer, and then focuses on the application of the chip in the multiplexer. Finally, the experience of using the CCS development simulator is introduced.

1 TS flow introduction

It mainly includes grouping method, program special information (PSI) table, and extraction of program reference clock (PCR).

(1) Grouping method

The transport stream packet length is fixed to 188 bytes, and the packet consists of the packet header and the payload, as shown in Figure 1.

(2) PSI

The PSI is divided into four categories of tables. As shown in Table 1, each table can be divided into one or more segments placed in the transport stream. The four types of tables are a program association table (PAT), a program map table (PMT), a network information table (NIT), and a conditional access table (CAT). These four types of tables contain the necessary and sufficient information to perform demultiplexing and display procedures.

Table 1 Program special information

System layer demultiplexing, first to get the PAT table. The PAT table contains a list of all the programs in the transport stream. Through the PAT table, the PMT table for each program included in the transfer can be obtained.

In the PMT table of each program, there is information about each original stream in the program, including the PID, the original stream type, and the PID in the transport stream containing the valid PCR field in the program. Through the PAT and PMT tables, you can grasp the relationship between each program in the transport stream and the originals in each program.

(3) PCR

In the transport stream, the synchronous implementation of the decoding is based on the corresponding program reference time PCR value. PCR is a time stamp that encodes the timing of the bitstream itself, which can be derived from the common time base used by the PTS of the video and audio of the same program. Since each program has its own time base, each program containing a multi-program transport stream has separate PCR fields.

2 C5402 Introduction

The C5402 is a cost-effective fixed-point digital signal processor introduced by TI in October 1999. Its main features are as follows:

* Advanced retrofit Harvard architecture with an operating speed of up to 100 MIPS;

* Advanced multi-bus architecture, three 16-bit data memory buses and one program memory bus;

*40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two 40-bit accumulators;

* 1 17 × 17 multiplier and 1 40-bit dedicated adder, allowing 16-bit multiplication with (without) symbols;

* 8 auxiliary registers and 1 software stack, allowing the use of the industry's most advanced fixed-point DSP C compiler;

* Data / program addressing space 1M × 6bit, built-in 4K × 16bit ROM and 16K × 16bit RAM.

* Built-in programmable wait state generator, phase-locked loop clock generator, 2 multi-channel buffered serial ports, 1 8-bit parallel and external processor communication HPI port, 2 16-bit timers and 6-channel DMA control Device

* Low power consumption, working power supply has 3V and 1.8V (core use).

3 multiplexer hardware block diagram and process

The hardware block diagram of the multiplexer is shown in Figure 2.

(1) Synthetic control card (main card) process

Main card process: Mainly complete the implementation monitoring of 6 card processing, generate PSI and other information and send it periodically. The PSI information of the main card: the PID of the 6 PMTs and the PID numbers of the video, audio, and PCR input from each subcard are predetermined.

(2) Single TS stream processing card (subcard) process

Sub-card process: TS stream enters FIFO buffer, PSI information is extracted and code rate is calculated by DSP; relevant information is sent to synthesis processing card for analysis and synthesis; 1 channel video and 1 channel are extracted from input stream as needed Audio and PCR packages and change their PID to pre-specified. The daughter card functions as a simple stream analyzer and provides a single TS stream.

4 typical applications of C5402

Application of C5402 in the system: analysis of input TS stream; uniform interleaving of 6-way code stream and reset of PSI information; communication between main card and daughter card through C5402 HPI interface; using C5402 serial port and computer RS232 serial port is connected.

4.1 Input TS stream analysis

The DSP reads the TS stream from the FIFO into the internal RAM. As shown in FIG. 3, the PAT table is found according to the 13-bit PID number 0x000, and the PMT ID number and the NIT ID number are obtained in the PAT table; the video is obtained according to the PMT_PID. , audio, PCR PID number and other private information PID number; according to PCR_PID and pcr_flag, find the PCR packet; calculate the code rate according to the formula:

Where i', i'' are two adjacent PCR packets, a plurality of code rates are obtained, and then an arithmetic average is obtained to obtain an average code rate. The data is transmitted using the FIFO at a rate between 10 and 25 MB/s. Since the DSP processing capability is 100 MIPS, the amount of data transmitted by the DSP in the daughter card is 2 MB/s, and the coupling time is 0.1 to 0.2 s, so that the processing time is sufficient (0.8 to 0.9 s). The sub-card input FIFO is 8KB in size. When it is half full, the maximum DSP waiting time is (188/10 000)×6=0.1128ms. The filling amount of the FIFO is 0.112 8×1=0.112 KB, which is far from inputting the code stream. The input buffer of the daughter card is filled up and causes an overflow.

4.2 Code Stream Interleaving and PSI Information Configuration

In order to combine the TS streams input by the six sub-cards into one TS stream, the function of the main card DSP is to evenly interleave the 6 TS streams. The main card data is sent to the DSP internal RAM of the main card through the HPI, and then written to the external FIFO. Since the PIDs of the various code streams are called the same, it is necessary to reset the ID numbers of the TS streams. The master card generates a new PSI table according to all PIDs set in advance, and sends them to the external FIFO at regular intervals. The CPU of the main card runs at 100 MHz, the size of the output FIFO is 8 KB, and is transmitted at a fixed 5 MHz code rate. The data filled in the sub-card does not cause the main card to overflow. When the output buffer of the main card is not half full, the empty packet is filled so that the FIFO does not underflow.

According to the PSI information obtained by the analysis in the daughter card, one or more program streams can be extracted, and the PID number is changed to a predetermined one, and transmitted to the main card through the HPI communication interface.

4.3 HPI interface

The HPI (Host Port Interface) interface facilitates communication between the primary and daughter cards without the need for additional components. The HPI operation of the C5402 is 8-bit. When the C5402 runs at 100MHz, the communication speed can reach 25MB/s. The HPI interface has three 16-bit registers: HPIA (address register), HPID (data register), and HPIC (control register). The connection between the main card and the sub-card DSP chip is shown in Figure 4: HD0 ~ HD7 are 8-bit data lines, directly connected to the data line of the main device; HCS is the strobe signal; HDS1 ~ HDS2 is the data latch The signal, in the access period of the master device, controls the transmission of data, generally connected to the data strobe of the device; HR/W is the read/write signal; HCNTL0/HCNL1 is used by the host device to select which register of the HPI and the register to be accessed. Access type, connected to the address line of the master device. Since the HPI register is 16 bits, The HPI is connected to the master device only by an 8-bit data line. Therefore, HBIL determines whether the first byte or the second byte of the first access word is connected to the master device address line.

For the HPI operation, the control word is first written to the HPIC, then the address to be accessed is written to the HPIA, and finally the HPID is fetched, and the HPI memory block can be written or written to the HPI memory block. In addition, you can also choose HPIA automatic increase mode, write the initial address to HPIA, you can no longer operate HPIA, each time you access the data, the address will be automatically increased by 1, thus speeding up the access speed.

4.4 main card DSP and computer interface

In order to realize the system self-test, code rate and program information extraction and output, we communicate with the serial port of the computer through the serial port of the DSP. As shown in Figure 5, the asynchronous communication method is adopted. Among them, 75C189 and 75C188 are level conversion chips, and C5402 has 2 McBSPs (multi-channel buffer serial ports). McBSP provides a full-duplex communication system with dual-cache transmit registers and three-level receive registers that allow continuous data stream transfer with data lengths of 8, 12, 16, 20, 24, 32; A-law and μ- law companding, up to 128 channels of transmission and reception. Data is communicated to the peripheral via the McBSP via the DR and DX pins. The control signal is implemented by four pins of CLKX, CLKR, FSX, and FSR.

4.5 DSP program BOOTL0ADER implementation

BOOTLOADER is to load user code from the outside to the internal memory to speed up the operation at power-on. We use the C5402 external 8-bit parallel I/O port to implement the BOOTLOADER program. The C5402 reads the I/O port 0xffff, which stores the first address (data area) of the external memory. If the keyword 08 AA is read in this first address, 8-bit loading is performed; if 10AA, 16-bit loading is performed. The hardware system is to add a piece of 3.3V Flash, the program is burned into the Flash with the programmer.

5 C5402 software programming experience

(1) C language and assembly mixed programming

In the case that the computing power is not very tight, developing the DSP program in C language not only greatly speeds up the development of DSP, but also greatly enhances the readability and portability of the developed DSP program, and the program modification is also very convenient. The efficiency of the C code can be increased by using the optimization function of the C compiler.

Under normal circumstances, there are three kinds of C language and assembly mixed programming methods: 1 independently write C program and assembler; 2 directly embed assembly statements in the corresponding position of C language program; 3 compile C program to generate corresponding assembler, then Manual optimization and modification of the assembler. The assembler variables and constants can be accessed from the C program, or the C program variables can be accessed in the assembler.

(2) Prevention of pipeline conflicts

Pipeline operation is one of the key technologies for DSP to achieve high speed and high efficiency. The TMS320C54X uses deep and 6-stage pipeline operations, so pipeline conflicts are inevitable. In general, when a pipeline conflict occurs, the DSP automatically inserts a delayed anatomical conflict problem, but sometimes the programmer needs to solve by adjusting the order of the program statements or inserting a certain amount of NOP into the program. E.g:

STLM A, BRC

NOP

RPTB LOOP

Statement

LOOP

(3) Storage space should be correctly allocated

The C5402 has a total of 192K words of storage space, a 64K word program area, a 64K word data area, and a 64K word I/O area. When OVLY=0 of register PMST, the on-chip RAM is accessible in the data area and is inaccessible in the program area. When OVLY=1, the on-chip RAM is mapped to the program area and data area, but the data page (address from 0H~) 7FH) does not map to program space. We choose the latter mode in programming. The program and data are in the same on-chip RAM. The program and data intervals cannot overlap when writing CMD files.

(4) Use of instructions

The assembly of 1TMS320C54X has arithmetic instructions and program instructions, and the two types of instructions can be interchanged. The port commands PORTW and PORTR are used when the external port is operating.

2 With the DADST and DSADT instructions, you can perform 2 operations in one accumulator at the same time.

3 The use of DADD and DSUB can achieve 32 addition and subtraction.

4 Use CMPS, SACCD, SRCCD, STRCD four conditions to store instructions to reduce the overhead of conditional instructions; use MAX, MIN, FIRS, LMS to reduce the instruction cycle required for operations; use C54 parallel instructions to save multiple times Data storage to improve the efficiency of programming.

5 Make full use of *(IK) addressing (indicating the address to be accessed in the data area), which can reduce the use of auxiliary registers.

(5) use less functions and subroutine calls

Although the structured program brings convenience to software and debugging, the call and return of a function and subroutine will cause the C5402 to generate a pipeline refresh once, increasing the instruction cycle, so when the storage space is sufficient, the macro structure should be used more; The size of the program must be considered during programming, so functions and subroutines can also be used in cases where the processing speed of the device is not greatly affected.

(6) About the preparation of the interrupt service program

Interrupts have soft and hard interrupts. When writing an interrupt service routine, the most important thing is to place the interrupt vector table correctly. First set the IPTR in the PMST register, then put the INT to the specified position, the interrupt mode INTM=0; the corresponding bit of the interrupt enable register is set to 1.

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