With the continuous development of semiconductor technology and deep-pressure micro-process, the switching speed of IC has been increased from tens of MHZ to several hundred MHZ, even several GHz. In high-speed PCB design, engineers often encounter signal integrity problems such as false triggering, damped oscillation, overshoot, undershoot, and crosstalk. This article will explore their formation reasons, calculation methods and how to solve these problems using the IBIS simulation method in Allegro. 1 Signal Integrity Definition Signal Integrity (SI) refers to the signal quality on the signal line. Poor signal integrity is not caused by a single factor, but by a combination of factors in board-level design. Reasons for disrupting signal integrity include reflection, ringing, ground bounce, crosstalk, and so on. As the signal operating frequency continues to increase, signal integrity issues have become the focus of high-speed PCB engineers. 2 Reflection 2.1 Reflection Formation and Calculation The impedance discontinuity on the transmission line causes signal reflection. When the source and load impedances do not match, the load reflects a part of the voltage back to the source. Differential line transmission signals solve many problems. What is a differential signal? In layman's terms, the driver sends two equal-valued, inverted signals. The receiver compares the difference between the two voltages to determine whether the logic state is "0" or "1". The pair of lines carrying the differential signals is called a differential line. How to calculate the differential line impedance? The impedance of various differential signals is different, such as USB D + D-, differential line impedance is 90 ohm, 1394 differential line is 110 ohm, it is best to look at the specification or related information. There are many computational impedance tools, such as the polar si9000, the factors that affect the differential impedance, the wire width, the differential line spacing, the dielectric constant of the dielectric, the thickness of the dielectric (the thickness of the dielectric between the differential and the reference plane), and generally the differential Line spacing and line width to control the differential impedance. When doing the board, please tell the manufacturer which lines to control the impedance. A differential signal uses a value to represent the difference between two physical quantities. Strictly speaking, all voltage signals are differential because one voltage can only be relative to the other. In some systems, the system 'ground' is used as a voltage reference point. When 'ground' is used as a voltage measurement reference, this signal planning is called single-ended. We use this term because the signal is represented by the voltage on a single conductor. The first benefit of the differential signal is that because you are controlling the 'reference' voltage, you can easily identify small signals. In a ground-based, single-ended signaling scheme, the exact value of the measured signal depends on the consistency of the 'ground' within the system. The further the source and signal receiver are, the more likely they are to differ between the local voltage values. The value of the signal recovered from the differential signal is largely independent of the exact value of 'ground', but within a certain range. The second benefit of the differential signal is that it is highly immune to external electromagnetic interference (EMI). An interference source affects each end of the differential signal pair to the same extent. Since the PADSLOGIC voltage difference in PADS determines the signal value, this will ignore any similar interference that occurs on both conductors. In addition to being less sensitive to interference, differential signals generate less EMI than single-ended signals. The third advantage of the differential signal is that the timing is accurate. Because the switching change of the differential signal is located at the intersection of the two signals, unlike the ordinary single-ended signal, which depends on the high and low threshold voltages, it is less affected by the process and temperature. It can reduce the error in timing and is also more suitable for circuits with low amplitude signals. The currently popular LVDS (low voltage differenTIal signaling) refers to this small amplitude differential signaling technique. Differences can be ignored without crosstalk because their crosstalk results are offset at the final acceptance. In addition, the difference is balanced and the parallelism is only part of the balance. I think the coupling of differential pairs is still necessary. For the single-line matching, although the theory is very mature, the actual PCB line still has about 5% error (on a material, I have not done it myself). On the other hand, the differential line can be thought of as a self-loop system, or the signals on its two signal lines are related. Poor coupling can cause different interference from elsewhere, and for some interface circuits, the equal length of Allegro training differential pairs is an important factor in controlling line delay. Therefore, I think the differential line should be tightly coupled. For most current high speed PCB boards, it is advantageous to maintain good coupling. But I hope that you don't mistake the coupling for the necessary conditions of the differential pair, which sometimes limits the design idea. When doing high-speed design or analysis, you should not only know how most people do it, but also understand why others do it, and then understand and improve based on the experience of others, and constantly train their creative thinking skills. Matching is required, but the reason for matching is not reflection, but the degree of crosstalk interference. If the reduction is related to the matching method, if the string resistance is used, there is no effect, but if the grounding or power supply termination matching method is used, Because the line impedance of the two lines is reduced, the string winding is reduced... For PCB LAYOUT engineers, the most important thing is to ensure that these advantages of differential routing can be fully exploited in the actual routing. Perhaps anyone who has been exposed to Layout will understand the general requirements for differential traces. The pcb design is "equal length, equidistance." The equal length is to ensure that the two differential signals maintain the opposite polarity at all times, reducing the common mode component; the equidistance is mainly to ensure that the differential impedance of the two is consistent and the reflection is reduced. "As close as possible to the principle" is sometimes one of the requirements for differential routing. Differential traces can also be used in different signal layers, but this method is generally not recommended because differences in impedance, vias generated by different layers can disrupt the effects of differential mode transmission and introduce common mode noise. In addition, if the adjacent two layers are not tightly coupled, the ability of the differential traces to resist noise is reduced, but crosstalk is not an issue if the proper spacing from the surrounding traces is maintained. At normal frequencies (below GHz), EMI is not a serious problem. Experiments show that the differential traces of 500Mils have a radiation energy attenuation of 60dB beyond 3 meters, which is enough to meet the FCC's electromagnetic radiation standards. The designer does not have to worry too much about the electromagnetic incompatibility caused by insufficient coupling of the differential lines. But all these rules are not used to make a hard copy, and many engineers do not seem to understand the nature of high-speed differential signaling. The following focuses on several common pitfalls in PCB differential signaling design. Think that the differential traces must be close. Bringing the differential traces closer is nothing more than enhancing their coupling, both to improve immunity to noise and to take advantage of the opposite polarity of the magnetic field to counteract electromagnetic interference to the outside world. Although this practice is very beneficial in most cases, it is not absolute. If we can guarantee that they are fully shielded from external interference, then we do not need to let the strong coupling through each other to achieve anti-interference. And the purpose of suppressing EMI. How can we ensure that the differential traces have good isolation and shielding? Increasing the distance from other signal traces is one of the most basic ways. The electromagnetic field energy decreases with the square of the distance, and the general line spacing exceeds 4 times. When they are wide, the interference between them is extremely weak and can be neglected. In addition, the ground plane isolation can also be used for good shielding. This structure is often used in high-frequency (10G or more) IC package PCB design. It is called CPW structure and can guarantee strict differential impedance. Control (2Z0). It is considered that the differential signal does not require a ground plane as a return path, or that the differential traces provide a return path to each other. The cause of this misunderstanding is that it is confused by surface phenomena, or the understanding of the mechanism of high-speed signal transmission is not deep enough. Differential circuits are insensitive to similar ground bounce and other noise signals that may be present at the power and ground planes. The partial return cancellation of the ground plane does not mean that the differential circuit does not use the reference plane as the signal return path. In fact, in the signal reflow analysis, the mechanism of the differential trace is the same as that of the ordinary single-ended trace, that is, the high frequency signal is always The reflow is performed along the loop with the smallest inductance. The biggest difference is that in addition to the coupling to the ground, the differential lines have mutual coupling, and which one is strong, which becomes the main return path. In the PCB circuit design, the coupling between the differential traces is generally small, often only 10 to 20% of the coupling degree, and more is the coupling to the ground, so the main return path of the differential traces still exists in the ground plane. When the local plane is discontinuous, there is no reference plane, and the coupling between the differential traces will provide the main return path, although the discontinuity of the reference plane does not affect the common single-ended trace. It is serious, but it will reduce the quality of differential signals and increase EMI. Try to avoid it. Some designers believe that the reference plane below the differential trace can be removed to suppress some common-mode signals in differential transmission, but in theory this is not desirable, how is the impedance controlled? No common-mode signal is provided. The ground impedance loop is bound to cause EMI radiation, which is more harmful than good. It is considered more important to keep the equal spacing longer than the matching line length. In actual PCB layout, the requirements of differential design cannot often be met at the same time. Due to factors such as pin distribution, vias, and trace space, the wire length matching must be achieved by proper winding, but the result is necessarily that the partial regions of the differential pair cannot be parallel. PCB differential traces The most important rule in the design is the matching line length. Other rules can be flexibly processed according to the design requirements and practical applications.
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Built-in 3.6V rechargeable Batteries ( . The purpose of the batteries is to store the total electricity and memory setting
Resetting
If an abnormal display appears or the buttons produce no response, the instrument must be reset. To do this,
press the RESET button.
Display Mode
Entire LCD can be displayed for about 1 minute and then it automatically gets into Model. To transfer from
one mode to the other, press the FUNCTION button.
Mode 1: Time/Watt/Cost Display Display duration(how long) this device connect to power source.LCD on first line shows 0:00 with first two figures mean minutes(2 figures will occur while occur at 10 min) and the rest shows seconds. After 60mins, it displays 0:00 again with first two numbers meas hour(2 figures will occur at 10hours)and the rest shows minutes. The rest can be done in the same manner which means after 24 hours, it will re-caculate. LCD on second line displays current power which ranges in 0.0W 〜 9999W. LCD on third line displays the current electricity costs which ranges in O.Ocost 〜 9999cost. It will keep on O.OOcost before setting rate without other figures.
Mode 2: Time/Cumulative electrical quantity Display Display duration(how long) this device connect to power source.
LCD on first line shows 0:00 with first two figures mean minutes(2 figures will occur while occur at 10 min) and the rest shows seconds. After 60mins, it displays 0:00 again with first two numbers meas hour(2 figures will occur at 10hours)and the rest shows minutes. The rest can be done in the same manner which
means after 24 hours, it will re-caculate. LCD on second line displays current cumulative electrical quantity which ranges in 0.000KWH 〜 9999KWH without other figures. LCD on third line displays"DAY"- "1 'Will be showed on numerical part(the other three figures will be showed at carry) which means it has cumulated electrical quantity for 24hours(one day). The rest can be done in the same manner untill the maximal cumulative time of 9999 days.
Mode 3: TimeA^bltage/Frequency Display LCD on first line displays the same as Mode 1 dones. LCD on second line displays current voltage supply (v) which ranges in 0.0V 〜 9999V .LCD on third line displays current frequency (HZ) which ranges in 0.0HZ 〜 9999Hz without other figures.
Mode 4: Time/Current/Power Factor Display LCD on first line displays the same as Mode 1 dones.LCD on second line displays load current which ranges in 0.0000A 〜 9999A. LCD on third line displays current power factor which ranges in 0.00PF 〜 LOOPF without other figures.
Mode 5:Time/Minimum Power Display LCD on first line displays the same as Mode 1 dones. LCD on
second line displays the minimum power which ranges in 0.0W 〜 9999W. LCD on third line displays character of "Lo" without other figures.
Mode 6: Time/Maximal Power Display LCD on first line displays the same as Mode 1 dones. LCD on second line displays the maximal power which ranges in 0.0W 〜 9999W. LCD on third line displays character of "Hi" without other figures.
Mode 7: Time/Price Display LCD on first line displays the same as Mode 1 dones. LCD on third line displays the cost which ranges in O.OOCOST/KWH 〜 99.99COST/KWH without other figures.
Overload Display: When the power socket connects the load over 3680W, LCD on second line displays the''OVERLOAD[ with booming noise to warn the users,( 1918928,selectable choice)
Supplemental informations:
1: Except [OVERLOAD[ interface, LCD on first line display time in repitition within 24hours.
2: LCD on first line, second line or third line described in this intruction take section according to two black lines on LCD screen. Here it added for clarified purpose.
3. Mode 7 will directly occur while press down button "cost".
4. [UP"&"Down" are in no function under un-setting mode.
Setting Mode
1. Electricity price setting
After keeping COST button pressed lasting more than 3 seconds(LCD on third line display system defaults price, eg O.OOCOST/KWH ),the rendered content begins moving up and down which means that the device
has entered the setting mode. After that, press FUNCTION for swithing , then press "UP"and "DOWN" button again to set value which ranges in OO.OOCOST/KWH 〜 99.99COST/KWH. After setting all above, press COST to return to Mode7 or it will automatically return to Mode7 without any pressing after setting with data storage.